Abstract: "This paper analyzes which factors are important to consider when building a model of coherency overhead for a single-bus, shared memory multiprocessor. Three architectural features are examined: (1) the size of the coherency block, (2) cache size and (3) the type of bus operation use...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	Eggers, Susan J. (VerfasserIn)
Format:	Buch
Sprache:	English
Veröffentlicht:	Seattle, Wash. 1989
Schriftenreihe:	University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report 89,9,9
Schlagworte:	Cache memory Multiprocessors
Zusammenfassung:	Abstract: "This paper analyzes which factors are important to consider when building a model of coherency overhead for a single-bus, shared memory multiprocessor. Three architectural features are examined: (1) the size of the coherency block, (2) cache size and (3) the type of bus operation used to carry out a particular coherency function. The experiments judge the effect of each architectural parameter on model accuracy by selectively including it in a base model and then comparing the model's predictions of coherency overhead to the results of realistic multiprocessor simulations. The results indicate that coherency block size is critical to include in a model of coherency overhead This factor alone improves the accuracy of the base model by a factor of approximately 5 to 50, depending on the application. It brings model predictions to within an average of 9 percent of the realistic simulations. Cache size and the type of the coherency-related bus operation are less important, contributing a 1.5 percent (for 128K byte caches) and 6 percent improvement, respectively, averaged over all traces. The minimal benefit of incorporating cache size supports the infinite cache assumption often used in analytic models of coherency overhead.
Beschreibung:	31 S.