An intelligent cache memory chip suitable for logical inference:
Gespeichert in:
| Format: | Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Tokyo, Japan
1991
|
| Schriftenreihe: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report
709 |
| Schlagworte: | |
| Beschreibung: | 34 S. |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV010956046 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t | ||
| 008 | 960918s1991 |||| 00||| engod | ||
| 035 | |a (OCoLC)26483714 | ||
| 035 | |a (DE-599)BVBBV010956046 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91G | ||
| 245 | 1 | 0 | |a An intelligent cache memory chip suitable for logical inference |c by K. Yasuda ... |
| 264 | 1 | |a Tokyo, Japan |c 1991 | |
| 300 | |a 34 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 709 | |
| 650 | 4 | |a Cache memory | |
| 650 | 4 | |a Fifth generation computers | |
| 700 | 1 | |a Yasuda, Kenichi |e Sonstige |4 oth | |
| 830 | 0 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 709 |w (DE-604)BV010923438 |9 709 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-007328228 | ||
Datensatz im Suchindex
| _version_ | 1804125443217948672 |
|---|---|
| any_adam_object | |
| building | Verbundindex |
| bvnumber | BV010956046 |
| ctrlnum | (OCoLC)26483714 (DE-599)BVBBV010956046 |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00959nam a2200289 cb4500</leader><controlfield tag="001">BV010956046</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">960918s1991 |||| 00||| engod</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)26483714</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV010956046</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">An intelligent cache memory chip suitable for logical inference</subfield><subfield code="c">by K. Yasuda ...</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Tokyo, Japan</subfield><subfield code="c">1991</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">34 S.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report</subfield><subfield code="v">709</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Cache memory</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Fifth generation computers</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Yasuda, Kenichi</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report</subfield><subfield code="v">709</subfield><subfield code="w">(DE-604)BV010923438</subfield><subfield code="9">709</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-007328228</subfield></datafield></record></collection> |
| id | DE-604.BV010956046 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T18:01:38Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007328228 |
| oclc_num | 26483714 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | 34 S. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| record_format | marc |
| series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| spelling | An intelligent cache memory chip suitable for logical inference by K. Yasuda ... Tokyo, Japan 1991 34 S. txt rdacontent n rdamedia nc rdacarrier Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 709 Cache memory Fifth generation computers Yasuda, Kenichi Sonstige oth Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 709 (DE-604)BV010923438 709 |
| spellingShingle | An intelligent cache memory chip suitable for logical inference Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report Cache memory Fifth generation computers |
| title | An intelligent cache memory chip suitable for logical inference |
| title_auth | An intelligent cache memory chip suitable for logical inference |
| title_exact_search | An intelligent cache memory chip suitable for logical inference |
| title_full | An intelligent cache memory chip suitable for logical inference by K. Yasuda ... |
| title_fullStr | An intelligent cache memory chip suitable for logical inference by K. Yasuda ... |
| title_full_unstemmed | An intelligent cache memory chip suitable for logical inference by K. Yasuda ... |
| title_short | An intelligent cache memory chip suitable for logical inference |
| title_sort | an intelligent cache memory chip suitable for logical inference |
| topic | Cache memory Fifth generation computers |
| topic_facet | Cache memory Fifth generation computers |
| volume_link | (DE-604)BV010923438 |
| work_keys_str_mv | AT yasudakenichi anintelligentcachememorychipsuitableforlogicalinference |