Using subpages for cache coherency control in parallel database systems:
Abstract: "Increasing requirements such as higher transaction rates, shorter response times etc., make it necessary to parallelize existing database management systems and to implement them on multiprocessors. Shared memory multiprocessors are not arbitrarily scalable, and thus do not meet futu...
Gespeichert in:
1. Verfasser: | |
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Format: | Buch |
Sprache: | English |
Veröffentlicht: |
München
1994
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Schriftenreihe: | Technische Universität <München>: TUM-I
9411 |
Schlagworte: | |
Zusammenfassung: | Abstract: "Increasing requirements such as higher transaction rates, shorter response times etc., make it necessary to parallelize existing database management systems and to implement them on multiprocessors. Shared memory multiprocessors are not arbitrarily scalable, and thus do not meet future requirements. Therefore, it makes sense to implement databases on large-scale distributed memory multicomputers. This raises the problem how to implement a database cache which uses shared memory concepts extensively under such hardware architecture. In this paper we describe a solution for this problem by introducing a virtual database cache (VDBC). The VDBC is an algorithmic approach based on the lazy release consistency model used in virtual shared memory systems and on the transaction concept. Additionally, the VDBC uses pages subdivided into equal sized subpages to maintain concurrency control and cache coherency and to reduce data contention on often accessed pages. The advantage of using subpages instead of just pages or of records is to combine the simple coherency control method used by page-level locking with the reduction of data contention provided by record-level locking. Our approach is based on the assumption, that interprocessor communication is quite favorable as compared to I/O -- it is thus interesting to exchange subpages with other processors instead of reading them from disk." |
Beschreibung: | Literaturverz. S. 20 - 22 |
Beschreibung: | 22 S. graph. Darst. |
Internformat
MARC
LEADER | 00000nam a2200000 cb4500 | ||
---|---|---|---|
001 | BV009967266 | ||
003 | DE-604 | ||
005 | 20040416 | ||
007 | t | ||
008 | 941219s1994 gw d||| t||| 00||| eng d | ||
016 | 7 | |a 94287711X |2 DE-101 | |
035 | |a (OCoLC)35123086 | ||
035 | |a (DE-599)BVBBV009967266 | ||
040 | |a DE-604 |b ger |e rakwb | ||
041 | 0 | |a eng | |
044 | |a gw |c DE | ||
049 | |a DE-12 |a DE-91G | ||
088 | |a TUM I 9411 | ||
100 | 1 | |a Listl, Andreas |e Verfasser |4 aut | |
245 | 1 | 0 | |a Using subpages for cache coherency control in parallel database systems |c Andreas Listl |
264 | 1 | |a München |c 1994 | |
300 | |a 22 S. |b graph. Darst. | ||
336 | |b txt |2 rdacontent | ||
337 | |b n |2 rdamedia | ||
338 | |b nc |2 rdacarrier | ||
490 | 1 | |a Technische Universität <München>: TUM-I |v 9411 | |
490 | 1 | |a Sonderforschungsbereich Methoden und Werkzeuge für die Nutzung paralleler Rechnerarchitekturen:SFB-Bericht / A |v 1994,6 | |
500 | |a Literaturverz. S. 20 - 22 | ||
520 | 3 | |a Abstract: "Increasing requirements such as higher transaction rates, shorter response times etc., make it necessary to parallelize existing database management systems and to implement them on multiprocessors. Shared memory multiprocessors are not arbitrarily scalable, and thus do not meet future requirements. Therefore, it makes sense to implement databases on large-scale distributed memory multicomputers. This raises the problem how to implement a database cache which uses shared memory concepts extensively under such hardware architecture. In this paper we describe a solution for this problem by introducing a virtual database cache (VDBC). The VDBC is an algorithmic approach based on the lazy release consistency model used in virtual shared memory systems and on the transaction concept. Additionally, the VDBC uses pages subdivided into equal sized subpages to maintain concurrency control and cache coherency and to reduce data contention on often accessed pages. The advantage of using subpages instead of just pages or of records is to combine the simple coherency control method used by page-level locking with the reduction of data contention provided by record-level locking. Our approach is based on the assumption, that interprocessor communication is quite favorable as compared to I/O -- it is thus interesting to exchange subpages with other processors instead of reading them from disk." | |
650 | 4 | |a Cache memory | |
650 | 4 | |a Parallel processing (Electronic computers) | |
650 | 4 | |a Virtual storage (Computer science) | |
810 | 2 | |a A |t Sonderforschungsbereich Methoden und Werkzeuge für die Nutzung paralleler Rechnerarchitekturen:SFB-Bericht |v 1994,6 |w (DE-604)BV004627888 |9 1994,6 | |
830 | 0 | |a Technische Universität <München>: TUM-I |v 9411 |w (DE-604)BV006185376 |9 9411 | |
999 | |a oai:aleph.bib-bvb.de:BVB01-006605750 |
Datensatz im Suchindex
_version_ | 1804124339934593024 |
---|---|
any_adam_object | |
author | Listl, Andreas |
author_facet | Listl, Andreas |
author_role | aut |
author_sort | Listl, Andreas |
author_variant | a l al |
building | Verbundindex |
bvnumber | BV009967266 |
ctrlnum | (OCoLC)35123086 (DE-599)BVBBV009967266 |
format | Book |
fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02833nam a2200385 cb4500</leader><controlfield tag="001">BV009967266</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20040416 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">941219s1994 gw d||| t||| 00||| eng d</controlfield><datafield tag="016" ind1="7" ind2=" "><subfield code="a">94287711X</subfield><subfield code="2">DE-101</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)35123086</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV009967266</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">gw</subfield><subfield code="c">DE</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-12</subfield><subfield code="a">DE-91G</subfield></datafield><datafield tag="088" ind1=" " ind2=" "><subfield code="a">TUM I 9411</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Listl, Andreas</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Using subpages for cache coherency control in parallel database systems</subfield><subfield code="c">Andreas Listl</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">München</subfield><subfield code="c">1994</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">22 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Technische Universität <München>: TUM-I</subfield><subfield code="v">9411</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Sonderforschungsbereich Methoden und Werkzeuge für die Nutzung paralleler Rechnerarchitekturen:SFB-Bericht / A</subfield><subfield code="v">1994,6</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Literaturverz. S. 20 - 22</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">Abstract: "Increasing requirements such as higher transaction rates, shorter response times etc., make it necessary to parallelize existing database management systems and to implement them on multiprocessors. Shared memory multiprocessors are not arbitrarily scalable, and thus do not meet future requirements. Therefore, it makes sense to implement databases on large-scale distributed memory multicomputers. This raises the problem how to implement a database cache which uses shared memory concepts extensively under such hardware architecture. In this paper we describe a solution for this problem by introducing a virtual database cache (VDBC). The VDBC is an algorithmic approach based on the lazy release consistency model used in virtual shared memory systems and on the transaction concept. Additionally, the VDBC uses pages subdivided into equal sized subpages to maintain concurrency control and cache coherency and to reduce data contention on often accessed pages. The advantage of using subpages instead of just pages or of records is to combine the simple coherency control method used by page-level locking with the reduction of data contention provided by record-level locking. Our approach is based on the assumption, that interprocessor communication is quite favorable as compared to I/O -- it is thus interesting to exchange subpages with other processors instead of reading them from disk."</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Cache memory</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Parallel processing (Electronic computers)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Virtual storage (Computer science)</subfield></datafield><datafield tag="810" ind1="2" ind2=" "><subfield code="a">A</subfield><subfield code="t">Sonderforschungsbereich Methoden und Werkzeuge für die Nutzung paralleler Rechnerarchitekturen:SFB-Bericht</subfield><subfield code="v">1994,6</subfield><subfield code="w">(DE-604)BV004627888</subfield><subfield code="9">1994,6</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Technische Universität <München>: TUM-I</subfield><subfield code="v">9411</subfield><subfield code="w">(DE-604)BV006185376</subfield><subfield code="9">9411</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-006605750</subfield></datafield></record></collection> |
id | DE-604.BV009967266 |
illustrated | Illustrated |
indexdate | 2024-07-09T17:44:06Z |
institution | BVB |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006605750 |
oclc_num | 35123086 |
open_access_boolean | |
owner | DE-12 DE-91G DE-BY-TUM |
owner_facet | DE-12 DE-91G DE-BY-TUM |
physical | 22 S. graph. Darst. |
publishDate | 1994 |
publishDateSearch | 1994 |
publishDateSort | 1994 |
record_format | marc |
series | Technische Universität <München>: TUM-I |
series2 | Technische Universität <München>: TUM-I Sonderforschungsbereich Methoden und Werkzeuge für die Nutzung paralleler Rechnerarchitekturen:SFB-Bericht / A |
spelling | Listl, Andreas Verfasser aut Using subpages for cache coherency control in parallel database systems Andreas Listl München 1994 22 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Technische Universität <München>: TUM-I 9411 Sonderforschungsbereich Methoden und Werkzeuge für die Nutzung paralleler Rechnerarchitekturen:SFB-Bericht / A 1994,6 Literaturverz. S. 20 - 22 Abstract: "Increasing requirements such as higher transaction rates, shorter response times etc., make it necessary to parallelize existing database management systems and to implement them on multiprocessors. Shared memory multiprocessors are not arbitrarily scalable, and thus do not meet future requirements. Therefore, it makes sense to implement databases on large-scale distributed memory multicomputers. This raises the problem how to implement a database cache which uses shared memory concepts extensively under such hardware architecture. In this paper we describe a solution for this problem by introducing a virtual database cache (VDBC). The VDBC is an algorithmic approach based on the lazy release consistency model used in virtual shared memory systems and on the transaction concept. Additionally, the VDBC uses pages subdivided into equal sized subpages to maintain concurrency control and cache coherency and to reduce data contention on often accessed pages. The advantage of using subpages instead of just pages or of records is to combine the simple coherency control method used by page-level locking with the reduction of data contention provided by record-level locking. Our approach is based on the assumption, that interprocessor communication is quite favorable as compared to I/O -- it is thus interesting to exchange subpages with other processors instead of reading them from disk." Cache memory Parallel processing (Electronic computers) Virtual storage (Computer science) A Sonderforschungsbereich Methoden und Werkzeuge für die Nutzung paralleler Rechnerarchitekturen:SFB-Bericht 1994,6 (DE-604)BV004627888 1994,6 Technische Universität <München>: TUM-I 9411 (DE-604)BV006185376 9411 |
spellingShingle | Listl, Andreas Using subpages for cache coherency control in parallel database systems Technische Universität <München>: TUM-I Cache memory Parallel processing (Electronic computers) Virtual storage (Computer science) |
title | Using subpages for cache coherency control in parallel database systems |
title_auth | Using subpages for cache coherency control in parallel database systems |
title_exact_search | Using subpages for cache coherency control in parallel database systems |
title_full | Using subpages for cache coherency control in parallel database systems Andreas Listl |
title_fullStr | Using subpages for cache coherency control in parallel database systems Andreas Listl |
title_full_unstemmed | Using subpages for cache coherency control in parallel database systems Andreas Listl |
title_short | Using subpages for cache coherency control in parallel database systems |
title_sort | using subpages for cache coherency control in parallel database systems |
topic | Cache memory Parallel processing (Electronic computers) Virtual storage (Computer science) |
topic_facet | Cache memory Parallel processing (Electronic computers) Virtual storage (Computer science) |
volume_link | (DE-604)BV004627888 (DE-604)BV006185376 |
work_keys_str_mv | AT listlandreas usingsubpagesforcachecoherencycontrolinparalleldatabasesystems |