Fundamental characteristics of the snooping cache in a parallel inference machine:

Abstract: "The design concepts of the snooping cache for a Parallel Inference Machine (the PIM/c prototype) are discussed and the cache's performance is investigated in detail. The snooping cache control mechanism was implemented on a single VLSI chip, and embedded in the PIM/c prototype t...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Format: Buch
Sprache:English
Veröffentlicht: Tokyo, Japan 1991
Schriftenreihe:Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report 656
Schlagworte:
Zusammenfassung:Abstract: "The design concepts of the snooping cache for a Parallel Inference Machine (the PIM/c prototype) are discussed and the cache's performance is investigated in detail. The snooping cache control mechanism was implemented on a single VLSI chip, and embedded in the PIM/c prototype to evaluate its actual performance. As the focus of this evaluation using a real machine is to clarify the fundamental characteristics of the snooping cache, we carried out the experiments by controlling the various parameters of the cache access patterns, instead of running specific benchmark programs. The results of the performance evaluation proved advantages of the snooping cache protocol such as an invalidation scheme and inter-cache data transfer mechanism
Finally, the design features of the cache architecture are examined to find directions for further improvement.
Beschreibung:36 S. graph. Darst.

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