Robust design of digital circuits on foil /:
A practical guide to the theory and applications of TFT technologies and circuit designs for those in academia and in industry.
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Cambridge :
Cambridge University Press,
2016.
|
| Subjects: | |
| Online Access: | DE-862 DE-863 |
| Summary: | A practical guide to the theory and applications of TFT technologies and circuit designs for those in academia and in industry. |
| Physical Description: | 1 online resource |
| Bibliography: | Includes bibliographical references and index. |
| ISBN: | 9781316657706 1316657701 9781316657355 1316657353 9781316656303 1316656306 |
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MARC
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| 100 | 1 | |a Myny, Kris, |d 1980- |e author. |1 https://id.oclc.org/worldcat/entity/E39PCjCCC7R3g77D4ktv33tWj3 |0 http://id.loc.gov/authorities/names/n2016001528 | |
| 245 | 1 | 0 | |a Robust design of digital circuits on foil / |c Kris Myny, Jan Genoe, Wim Dehaene. |
| 260 | |a Cambridge : |b Cambridge University Press, |c 2016. | ||
| 300 | |a 1 online resource | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
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| 588 | 0 | |a Online resource; title from PDF title page (EBSCO, viewed September 19, 2016). | |
| 504 | |a Includes bibliographical references and index. | ||
| 505 | 0 | |a Cover; Half-title; Title page; Copyright information; Epigraph; Table of contents; Preface; List of abbreviations; 1 Thin-Film Transistor Technologies on the Move? From Backplane Driver to Ubiquitous Circuit Enabler?; 1.1 Backplanes for Active Matrix Displays; 1.1.1 Amorphous Silicon; 1.1.2 Low-Temperature Polycrystalline Silicon; 1.1.3 Organic Thin-Film Transistors; 1.1.4 Metal-Oxide Thin-Film Transistors; 1.1.5 Current TFT Technology Overview; 1.1.6 Options for Flexible Displays; 1.2 Large Area Sensors and Circuits (On Foil); 2 Organic and Metal-Oxide Thin-Film Transistors. | |
| 505 | 8 | |a 2.1 Device Configurations2.2 Operation Principle; 2.2.1 Operation Principle of a Single-Gate Transistor; 2.2.2 Technology Options for Multiple Threshold Voltages; 2.3 Typical Layout Rules in the Technologies Used in This Book; 2.4 Technologies Used in This Book; 2.4.1 Organic p-Type Technology of Polymer Vision; 2.4.2 Organic p-Type Dual-Gate Technology of Polymer Vision; 2.4.3 Pentacene (p-Type) Thin-Film Transistors on Al2O3 as Gate Dielectric; 2.4.4 a-IGZO (n-Type) Technology on Al2O3 as Gate Dielectric; 2.4.5 Hybrid Complementary Organic/Metal-Oxide Technology. | |
| 505 | 8 | |a 2.4.6 Hybrid Complementary Organic/Metal-Oxide Technology on PEN-Foil2.5 Trends in Circuit Integration; 2.5.1 Display Periphery; 2.5.2 Digital Logic; 2.5.3 Analog Circuits; 2.6 Summary; 3 Basic Gates; 3.1 Figures-of-Merit; 3.2 Logic Families; 3.3 Unipolar Logic; 3.3.1 Single VT, Depletion-Load, or Zero-VGS-Load Logic; 3.3.1.1 VTC of the Zero-VGS-Load Inverter; 3.3.1.2 Static Parameters of the Zero-VGS-Load Inverter; VM; Gain; 3.3.1.3 Dynamic Behavior of the Zero-VGS-Load Inverter; Study of the Zero-VGS-Load Capacitors; 3.3.2 Dual VT, Zero-VGS-Load Logic by Dual-Gate TFTs. | |
| 505 | 8 | |a 3.3.2.1 VTC of a Dual-VT Zero-VGS-Load Inverter3.3.2.2 Dual-Gate Zero-VGS-Load Inverter; 3.3.2.3 Optimized Dual-Gate Zero-VGS-Load Inverter; 3.3.3 Single VT, Enhancement-Load, or Diode-Load Logic; 3.3.3.1 VTC of the Diode-Load Inverter; 3.3.3.2 Static Behavior of the Diode-Load Inverter; VM; Gain; 3.3.3.3 Dynamic Behavior of the Diode-Load Inverter; Study of the Diode-Load Capacitances; 3.3.4 Dual VT, Diode-Load Logic in Dual-Gate Technologies; 3.4 Complementary Logic; 3.4.1 VTC of the Complementary Inverter; 3.4.2 Static Behavior of the Complementary Inverter; 3.4.2.1 VM; 3.4.2.2 Gain. | |
| 505 | 8 | |a 3.4.3 Dynamic Behavior of the Complementary Inverter3.4.3.1 Study of the Complementary Inverter Capacitances; 3.5 Conclusions; 3.6 Suggestions to Improve the Inverter Performance; 3.6.1 Level-Shifter; 3.6.2 Self-Aligned Technology; 4 Variability; 4.1 Classifications; 4.2 Sources of Process Variation; 4.2.1 Semiconductor; 4.2.1.1 Dielectric; 4.2.2 Contacts; 4.2.3 Foil; 4.3 Influence of Parameter Variation on the Yield of Logic Circuits; 4.4 How to Cope with WID and D2D Parameter Variations; 4.4.1 Designing with WID Variations; 4.4.2 Designing with D2D Variations -- Corner Analysis. | |
| 520 | |a A practical guide to the theory and applications of TFT technologies and circuit designs for those in academia and in industry. | ||
| 650 | 0 | |a Logic circuits. |0 http://id.loc.gov/authorities/subjects/sh85078116 | |
| 650 | 0 | |a Flexible electronics |x Materials. | |
| 650 | 0 | |a Thin film transistors. |0 http://id.loc.gov/authorities/subjects/sh93004730 | |
| 650 | 0 | |a Digital electronics. |0 http://id.loc.gov/authorities/subjects/sh85037976 | |
| 650 | 0 | |a Metal foils. |0 http://id.loc.gov/authorities/subjects/sh85084056 | |
| 650 | 6 | |a Circuits logiques. | |
| 650 | 6 | |a Électronique flexible |x Matériaux. | |
| 650 | 6 | |a Transistors à couches minces. | |
| 650 | 6 | |a Électronique numérique. | |
| 650 | 6 | |a Feuilles de métal. | |
| 650 | 7 | |a foil (metal by form) |2 aat | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Mechanical. |2 bisacsh | |
| 650 | 7 | |a Digital electronics |2 fast | |
| 650 | 7 | |a Logic circuits |2 fast | |
| 650 | 7 | |a Metal foils |2 fast | |
| 650 | 7 | |a Thin film transistors |2 fast | |
| 655 | 0 | |a Electronic books. | |
| 700 | 1 | |a Genoe, Jan, |d 1965- |e author. |1 https://id.oclc.org/worldcat/entity/E39PCjKJkYP8W3bxtrxXg6k79C |0 http://id.loc.gov/authorities/names/n2016001525 | |
| 700 | 1 | |a Dehaene, Wim, |e author. |1 https://id.oclc.org/worldcat/entity/E39PCjJYfDfWjJ3Mw49d4wTPwC |0 http://id.loc.gov/authorities/names/nb2009020730 | |
| 776 | 0 | 8 | |i Print version: |a Myny, Kris, 1980- |t Robust design of digital circuits on foil. |d Cambridge : Cambridge University Press, 2016 |z 9781107127012 |z 1107127017 |w (DLC) 2015047185 |w (OCoLC)933713815 |
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Record in the Search Index
| DE-BY-FWS_katkey | ZDB-4-EBA-ocn958454885 |
|---|---|
| _version_ | 1829095081017081856 |
| adam_text | |
| any_adam_object | |
| author | Myny, Kris, 1980- Genoe, Jan, 1965- Dehaene, Wim |
| author_GND | http://id.loc.gov/authorities/names/n2016001528 http://id.loc.gov/authorities/names/n2016001525 http://id.loc.gov/authorities/names/nb2009020730 |
| author_facet | Myny, Kris, 1980- Genoe, Jan, 1965- Dehaene, Wim |
| author_role | aut aut aut |
| author_sort | Myny, Kris, 1980- |
| author_variant | k m km j g jg w d wd |
| building | Verbundindex |
| bvnumber | localFWS |
| callnumber-first | T - Technology |
| callnumber-label | TK7868 |
| callnumber-raw | TK7868.L6 M96 2016 |
| callnumber-search | TK7868.L6 M96 2016 |
| callnumber-sort | TK 47868 L6 M96 42016 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| collection | ZDB-4-EBA |
| contents | Cover; Half-title; Title page; Copyright information; Epigraph; Table of contents; Preface; List of abbreviations; 1 Thin-Film Transistor Technologies on the Move? From Backplane Driver to Ubiquitous Circuit Enabler?; 1.1 Backplanes for Active Matrix Displays; 1.1.1 Amorphous Silicon; 1.1.2 Low-Temperature Polycrystalline Silicon; 1.1.3 Organic Thin-Film Transistors; 1.1.4 Metal-Oxide Thin-Film Transistors; 1.1.5 Current TFT Technology Overview; 1.1.6 Options for Flexible Displays; 1.2 Large Area Sensors and Circuits (On Foil); 2 Organic and Metal-Oxide Thin-Film Transistors. 2.1 Device Configurations2.2 Operation Principle; 2.2.1 Operation Principle of a Single-Gate Transistor; 2.2.2 Technology Options for Multiple Threshold Voltages; 2.3 Typical Layout Rules in the Technologies Used in This Book; 2.4 Technologies Used in This Book; 2.4.1 Organic p-Type Technology of Polymer Vision; 2.4.2 Organic p-Type Dual-Gate Technology of Polymer Vision; 2.4.3 Pentacene (p-Type) Thin-Film Transistors on Al2O3 as Gate Dielectric; 2.4.4 a-IGZO (n-Type) Technology on Al2O3 as Gate Dielectric; 2.4.5 Hybrid Complementary Organic/Metal-Oxide Technology. 2.4.6 Hybrid Complementary Organic/Metal-Oxide Technology on PEN-Foil2.5 Trends in Circuit Integration; 2.5.1 Display Periphery; 2.5.2 Digital Logic; 2.5.3 Analog Circuits; 2.6 Summary; 3 Basic Gates; 3.1 Figures-of-Merit; 3.2 Logic Families; 3.3 Unipolar Logic; 3.3.1 Single VT, Depletion-Load, or Zero-VGS-Load Logic; 3.3.1.1 VTC of the Zero-VGS-Load Inverter; 3.3.1.2 Static Parameters of the Zero-VGS-Load Inverter; VM; Gain; 3.3.1.3 Dynamic Behavior of the Zero-VGS-Load Inverter; Study of the Zero-VGS-Load Capacitors; 3.3.2 Dual VT, Zero-VGS-Load Logic by Dual-Gate TFTs. 3.3.2.1 VTC of a Dual-VT Zero-VGS-Load Inverter3.3.2.2 Dual-Gate Zero-VGS-Load Inverter; 3.3.2.3 Optimized Dual-Gate Zero-VGS-Load Inverter; 3.3.3 Single VT, Enhancement-Load, or Diode-Load Logic; 3.3.3.1 VTC of the Diode-Load Inverter; 3.3.3.2 Static Behavior of the Diode-Load Inverter; VM; Gain; 3.3.3.3 Dynamic Behavior of the Diode-Load Inverter; Study of the Diode-Load Capacitances; 3.3.4 Dual VT, Diode-Load Logic in Dual-Gate Technologies; 3.4 Complementary Logic; 3.4.1 VTC of the Complementary Inverter; 3.4.2 Static Behavior of the Complementary Inverter; 3.4.2.1 VM; 3.4.2.2 Gain. 3.4.3 Dynamic Behavior of the Complementary Inverter3.4.3.1 Study of the Complementary Inverter Capacitances; 3.5 Conclusions; 3.6 Suggestions to Improve the Inverter Performance; 3.6.1 Level-Shifter; 3.6.2 Self-Aligned Technology; 4 Variability; 4.1 Classifications; 4.2 Sources of Process Variation; 4.2.1 Semiconductor; 4.2.1.1 Dielectric; 4.2.2 Contacts; 4.2.3 Foil; 4.3 Influence of Parameter Variation on the Yield of Logic Circuits; 4.4 How to Cope with WID and D2D Parameter Variations; 4.4.1 Designing with WID Variations; 4.4.2 Designing with D2D Variations -- Corner Analysis. |
| ctrlnum | (OCoLC)958454885 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| genre | Electronic books. |
| genre_facet | Electronic books. |
| id | ZDB-4-EBA-ocn958454885 |
| illustrated | Not Illustrated |
| indexdate | 2025-04-11T08:43:20Z |
| institution | BVB |
| isbn | 9781316657706 1316657701 9781316657355 1316657353 9781316656303 1316656306 |
| language | English |
| oclc_num | 958454885 |
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| physical | 1 online resource |
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| publishDate | 2016 |
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| publisher | Cambridge University Press, |
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| spelling | Myny, Kris, 1980- author. https://id.oclc.org/worldcat/entity/E39PCjCCC7R3g77D4ktv33tWj3 http://id.loc.gov/authorities/names/n2016001528 Robust design of digital circuits on foil / Kris Myny, Jan Genoe, Wim Dehaene. Cambridge : Cambridge University Press, 2016. 1 online resource text txt rdacontent computer c rdamedia online resource cr rdacarrier Online resource; title from PDF title page (EBSCO, viewed September 19, 2016). Includes bibliographical references and index. Cover; Half-title; Title page; Copyright information; Epigraph; Table of contents; Preface; List of abbreviations; 1 Thin-Film Transistor Technologies on the Move? From Backplane Driver to Ubiquitous Circuit Enabler?; 1.1 Backplanes for Active Matrix Displays; 1.1.1 Amorphous Silicon; 1.1.2 Low-Temperature Polycrystalline Silicon; 1.1.3 Organic Thin-Film Transistors; 1.1.4 Metal-Oxide Thin-Film Transistors; 1.1.5 Current TFT Technology Overview; 1.1.6 Options for Flexible Displays; 1.2 Large Area Sensors and Circuits (On Foil); 2 Organic and Metal-Oxide Thin-Film Transistors. 2.1 Device Configurations2.2 Operation Principle; 2.2.1 Operation Principle of a Single-Gate Transistor; 2.2.2 Technology Options for Multiple Threshold Voltages; 2.3 Typical Layout Rules in the Technologies Used in This Book; 2.4 Technologies Used in This Book; 2.4.1 Organic p-Type Technology of Polymer Vision; 2.4.2 Organic p-Type Dual-Gate Technology of Polymer Vision; 2.4.3 Pentacene (p-Type) Thin-Film Transistors on Al2O3 as Gate Dielectric; 2.4.4 a-IGZO (n-Type) Technology on Al2O3 as Gate Dielectric; 2.4.5 Hybrid Complementary Organic/Metal-Oxide Technology. 2.4.6 Hybrid Complementary Organic/Metal-Oxide Technology on PEN-Foil2.5 Trends in Circuit Integration; 2.5.1 Display Periphery; 2.5.2 Digital Logic; 2.5.3 Analog Circuits; 2.6 Summary; 3 Basic Gates; 3.1 Figures-of-Merit; 3.2 Logic Families; 3.3 Unipolar Logic; 3.3.1 Single VT, Depletion-Load, or Zero-VGS-Load Logic; 3.3.1.1 VTC of the Zero-VGS-Load Inverter; 3.3.1.2 Static Parameters of the Zero-VGS-Load Inverter; VM; Gain; 3.3.1.3 Dynamic Behavior of the Zero-VGS-Load Inverter; Study of the Zero-VGS-Load Capacitors; 3.3.2 Dual VT, Zero-VGS-Load Logic by Dual-Gate TFTs. 3.3.2.1 VTC of a Dual-VT Zero-VGS-Load Inverter3.3.2.2 Dual-Gate Zero-VGS-Load Inverter; 3.3.2.3 Optimized Dual-Gate Zero-VGS-Load Inverter; 3.3.3 Single VT, Enhancement-Load, or Diode-Load Logic; 3.3.3.1 VTC of the Diode-Load Inverter; 3.3.3.2 Static Behavior of the Diode-Load Inverter; VM; Gain; 3.3.3.3 Dynamic Behavior of the Diode-Load Inverter; Study of the Diode-Load Capacitances; 3.3.4 Dual VT, Diode-Load Logic in Dual-Gate Technologies; 3.4 Complementary Logic; 3.4.1 VTC of the Complementary Inverter; 3.4.2 Static Behavior of the Complementary Inverter; 3.4.2.1 VM; 3.4.2.2 Gain. 3.4.3 Dynamic Behavior of the Complementary Inverter3.4.3.1 Study of the Complementary Inverter Capacitances; 3.5 Conclusions; 3.6 Suggestions to Improve the Inverter Performance; 3.6.1 Level-Shifter; 3.6.2 Self-Aligned Technology; 4 Variability; 4.1 Classifications; 4.2 Sources of Process Variation; 4.2.1 Semiconductor; 4.2.1.1 Dielectric; 4.2.2 Contacts; 4.2.3 Foil; 4.3 Influence of Parameter Variation on the Yield of Logic Circuits; 4.4 How to Cope with WID and D2D Parameter Variations; 4.4.1 Designing with WID Variations; 4.4.2 Designing with D2D Variations -- Corner Analysis. A practical guide to the theory and applications of TFT technologies and circuit designs for those in academia and in industry. Logic circuits. http://id.loc.gov/authorities/subjects/sh85078116 Flexible electronics Materials. Thin film transistors. http://id.loc.gov/authorities/subjects/sh93004730 Digital electronics. http://id.loc.gov/authorities/subjects/sh85037976 Metal foils. http://id.loc.gov/authorities/subjects/sh85084056 Circuits logiques. Électronique flexible Matériaux. Transistors à couches minces. Électronique numérique. Feuilles de métal. foil (metal by form) aat TECHNOLOGY & ENGINEERING Mechanical. bisacsh Digital electronics fast Logic circuits fast Metal foils fast Thin film transistors fast Electronic books. Genoe, Jan, 1965- author. https://id.oclc.org/worldcat/entity/E39PCjKJkYP8W3bxtrxXg6k79C http://id.loc.gov/authorities/names/n2016001525 Dehaene, Wim, author. https://id.oclc.org/worldcat/entity/E39PCjJYfDfWjJ3Mw49d4wTPwC http://id.loc.gov/authorities/names/nb2009020730 Print version: Myny, Kris, 1980- Robust design of digital circuits on foil. Cambridge : Cambridge University Press, 2016 9781107127012 1107127017 (DLC) 2015047185 (OCoLC)933713815 |
| spellingShingle | Myny, Kris, 1980- Genoe, Jan, 1965- Dehaene, Wim Robust design of digital circuits on foil / Cover; Half-title; Title page; Copyright information; Epigraph; Table of contents; Preface; List of abbreviations; 1 Thin-Film Transistor Technologies on the Move? From Backplane Driver to Ubiquitous Circuit Enabler?; 1.1 Backplanes for Active Matrix Displays; 1.1.1 Amorphous Silicon; 1.1.2 Low-Temperature Polycrystalline Silicon; 1.1.3 Organic Thin-Film Transistors; 1.1.4 Metal-Oxide Thin-Film Transistors; 1.1.5 Current TFT Technology Overview; 1.1.6 Options for Flexible Displays; 1.2 Large Area Sensors and Circuits (On Foil); 2 Organic and Metal-Oxide Thin-Film Transistors. 2.1 Device Configurations2.2 Operation Principle; 2.2.1 Operation Principle of a Single-Gate Transistor; 2.2.2 Technology Options for Multiple Threshold Voltages; 2.3 Typical Layout Rules in the Technologies Used in This Book; 2.4 Technologies Used in This Book; 2.4.1 Organic p-Type Technology of Polymer Vision; 2.4.2 Organic p-Type Dual-Gate Technology of Polymer Vision; 2.4.3 Pentacene (p-Type) Thin-Film Transistors on Al2O3 as Gate Dielectric; 2.4.4 a-IGZO (n-Type) Technology on Al2O3 as Gate Dielectric; 2.4.5 Hybrid Complementary Organic/Metal-Oxide Technology. 2.4.6 Hybrid Complementary Organic/Metal-Oxide Technology on PEN-Foil2.5 Trends in Circuit Integration; 2.5.1 Display Periphery; 2.5.2 Digital Logic; 2.5.3 Analog Circuits; 2.6 Summary; 3 Basic Gates; 3.1 Figures-of-Merit; 3.2 Logic Families; 3.3 Unipolar Logic; 3.3.1 Single VT, Depletion-Load, or Zero-VGS-Load Logic; 3.3.1.1 VTC of the Zero-VGS-Load Inverter; 3.3.1.2 Static Parameters of the Zero-VGS-Load Inverter; VM; Gain; 3.3.1.3 Dynamic Behavior of the Zero-VGS-Load Inverter; Study of the Zero-VGS-Load Capacitors; 3.3.2 Dual VT, Zero-VGS-Load Logic by Dual-Gate TFTs. 3.3.2.1 VTC of a Dual-VT Zero-VGS-Load Inverter3.3.2.2 Dual-Gate Zero-VGS-Load Inverter; 3.3.2.3 Optimized Dual-Gate Zero-VGS-Load Inverter; 3.3.3 Single VT, Enhancement-Load, or Diode-Load Logic; 3.3.3.1 VTC of the Diode-Load Inverter; 3.3.3.2 Static Behavior of the Diode-Load Inverter; VM; Gain; 3.3.3.3 Dynamic Behavior of the Diode-Load Inverter; Study of the Diode-Load Capacitances; 3.3.4 Dual VT, Diode-Load Logic in Dual-Gate Technologies; 3.4 Complementary Logic; 3.4.1 VTC of the Complementary Inverter; 3.4.2 Static Behavior of the Complementary Inverter; 3.4.2.1 VM; 3.4.2.2 Gain. 3.4.3 Dynamic Behavior of the Complementary Inverter3.4.3.1 Study of the Complementary Inverter Capacitances; 3.5 Conclusions; 3.6 Suggestions to Improve the Inverter Performance; 3.6.1 Level-Shifter; 3.6.2 Self-Aligned Technology; 4 Variability; 4.1 Classifications; 4.2 Sources of Process Variation; 4.2.1 Semiconductor; 4.2.1.1 Dielectric; 4.2.2 Contacts; 4.2.3 Foil; 4.3 Influence of Parameter Variation on the Yield of Logic Circuits; 4.4 How to Cope with WID and D2D Parameter Variations; 4.4.1 Designing with WID Variations; 4.4.2 Designing with D2D Variations -- Corner Analysis. Logic circuits. http://id.loc.gov/authorities/subjects/sh85078116 Flexible electronics Materials. Thin film transistors. http://id.loc.gov/authorities/subjects/sh93004730 Digital electronics. http://id.loc.gov/authorities/subjects/sh85037976 Metal foils. http://id.loc.gov/authorities/subjects/sh85084056 Circuits logiques. Électronique flexible Matériaux. Transistors à couches minces. Électronique numérique. Feuilles de métal. foil (metal by form) aat TECHNOLOGY & ENGINEERING Mechanical. bisacsh Digital electronics fast Logic circuits fast Metal foils fast Thin film transistors fast |
| subject_GND | http://id.loc.gov/authorities/subjects/sh85078116 http://id.loc.gov/authorities/subjects/sh93004730 http://id.loc.gov/authorities/subjects/sh85037976 http://id.loc.gov/authorities/subjects/sh85084056 |
| title | Robust design of digital circuits on foil / |
| title_auth | Robust design of digital circuits on foil / |
| title_exact_search | Robust design of digital circuits on foil / |
| title_full | Robust design of digital circuits on foil / Kris Myny, Jan Genoe, Wim Dehaene. |
| title_fullStr | Robust design of digital circuits on foil / Kris Myny, Jan Genoe, Wim Dehaene. |
| title_full_unstemmed | Robust design of digital circuits on foil / Kris Myny, Jan Genoe, Wim Dehaene. |
| title_short | Robust design of digital circuits on foil / |
| title_sort | robust design of digital circuits on foil |
| topic | Logic circuits. http://id.loc.gov/authorities/subjects/sh85078116 Flexible electronics Materials. Thin film transistors. http://id.loc.gov/authorities/subjects/sh93004730 Digital electronics. http://id.loc.gov/authorities/subjects/sh85037976 Metal foils. http://id.loc.gov/authorities/subjects/sh85084056 Circuits logiques. Électronique flexible Matériaux. Transistors à couches minces. Électronique numérique. Feuilles de métal. foil (metal by form) aat TECHNOLOGY & ENGINEERING Mechanical. bisacsh Digital electronics fast Logic circuits fast Metal foils fast Thin film transistors fast |
| topic_facet | Logic circuits. Flexible electronics Materials. Thin film transistors. Digital electronics. Metal foils. Circuits logiques. Électronique flexible Matériaux. Transistors à couches minces. Électronique numérique. Feuilles de métal. foil (metal by form) TECHNOLOGY & ENGINEERING Mechanical. Digital electronics Logic circuits Metal foils Thin film transistors Electronic books. |
| work_keys_str_mv | AT mynykris robustdesignofdigitalcircuitsonfoil AT genoejan robustdesignofdigitalcircuitsonfoil AT dehaenewim robustdesignofdigitalcircuitsonfoil |