VLSI physical design: From graph partitioning to timing closure:
Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Cham
Springer
[2022]
|
| Edition: | Second edition |
| Subjects: | |
| Physical Description: | xvii, 317 Seiten Illustrationen, Diagramme (überwiegend farbig) |
| ISBN: | 9783030964146 |
Staff View
MARC
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| 245 | 1 | 0 | |a VLSI physical design: From graph partitioning to timing closure |c Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu |
| 246 | 1 | 3 | |a Very large-scale integration design: from graph partitioning to timing closure |
| 250 | |a Second edition | ||
| 264 | 1 | |a Cham |b Springer |c [2022] | |
| 264 | 4 | |c © 2022 | |
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| 650 | 4 | |a Electronic Circuits and Systems | |
| 650 | 4 | |a Logic Design | |
| 650 | 4 | |a Electronics and Microelectronics, Instrumentation | |
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Record in the Search Index
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| author | Kahng, Andrew B. 1963- Lienig, Jens 196X- Markov, Igor L. 1973- Hu, Jin |
| author_GND | (DE-588)143791435 (DE-588)113008740 (DE-588)137299354 |
| author_facet | Kahng, Andrew B. 1963- Lienig, Jens 196X- Markov, Igor L. 1973- Hu, Jin |
| author_role | aut aut aut aut |
| author_sort | Kahng, Andrew B. 1963- |
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| bvnumber | BV048630015 |
| classification_rvk | ZN 4952 ST 190 |
| classification_tum | ELT 355 |
| ctrlnum | (OCoLC)1392144490 (DE-599)BVBBV048630015 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik Maschinenbau |
| edition | Second edition |
| format | Book |
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| id | DE-604.BV048630015 |
| illustrated | Illustrated |
| index_date | 2024-07-03T21:15:50Z |
| indexdate | 2024-10-14T08:00:47Z |
| institution | BVB |
| isbn | 9783030964146 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-034005074 |
| oclc_num | 1392144490 |
| open_access_boolean | |
| owner | DE-11 DE-83 DE-91 DE-BY-TUM |
| owner_facet | DE-11 DE-83 DE-91 DE-BY-TUM |
| physical | xvii, 317 Seiten Illustrationen, Diagramme (überwiegend farbig) |
| publishDate | 2022 |
| publishDateSearch | 2022 |
| publishDateSort | 2022 |
| publisher | Springer |
| record_format | marc |
| spelling | Kahng, Andrew B. 1963- Verfasser (DE-588)143791435 aut VLSI physical design: From graph partitioning to timing closure Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu Very large-scale integration design: from graph partitioning to timing closure Second edition Cham Springer [2022] © 2022 xvii, 317 Seiten Illustrationen, Diagramme (überwiegend farbig) txt rdacontent n rdamedia nc rdacarrier Electronic Circuits and Systems Logic Design Electronics and Microelectronics, Instrumentation Computer-Aided Engineering (CAD, CAE) and Design Electronic circuits Logic design Electronics Computer-aided engineering Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Schaltungsentwurf (DE-588)4179389-4 s DE-604 Lienig, Jens 196X- (DE-588)113008740 aut Markov, Igor L. 1973- (DE-588)137299354 aut Hu, Jin aut Erscheint auch als Online-Ausgabe 978-3-030-96415-3 |
| spellingShingle | Kahng, Andrew B. 1963- Lienig, Jens 196X- Markov, Igor L. 1973- Hu, Jin VLSI physical design: From graph partitioning to timing closure Electronic Circuits and Systems Logic Design Electronics and Microelectronics, Instrumentation Computer-Aided Engineering (CAD, CAE) and Design Electronic circuits Logic design Electronics Computer-aided engineering Schaltungsentwurf (DE-588)4179389-4 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4179389-4 (DE-588)4117388-0 |
| title | VLSI physical design: From graph partitioning to timing closure |
| title_alt | Very large-scale integration design: from graph partitioning to timing closure |
| title_auth | VLSI physical design: From graph partitioning to timing closure |
| title_exact_search | VLSI physical design: From graph partitioning to timing closure |
| title_exact_search_txtP | VLSI physical design: From graph partitioning to timing closure |
| title_full | VLSI physical design: From graph partitioning to timing closure Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu |
| title_fullStr | VLSI physical design: From graph partitioning to timing closure Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu |
| title_full_unstemmed | VLSI physical design: From graph partitioning to timing closure Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu |
| title_short | VLSI physical design: From graph partitioning to timing closure |
| title_sort | vlsi physical design from graph partitioning to timing closure |
| topic | Electronic Circuits and Systems Logic Design Electronics and Microelectronics, Instrumentation Computer-Aided Engineering (CAD, CAE) and Design Electronic circuits Logic design Electronics Computer-aided engineering Schaltungsentwurf (DE-588)4179389-4 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Electronic Circuits and Systems Logic Design Electronics and Microelectronics, Instrumentation Computer-Aided Engineering (CAD, CAE) and Design Electronic circuits Logic design Electronics Computer-aided engineering Schaltungsentwurf VLSI |
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