Logic design and verification using SystemVerilog:
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Pittsburgh, PA
Donald Thomas
[2016]
|
| Edition: | Revised |
| Subjects: | |
| Physical Description: | xxii, 311 Seiten Diagramme |
| ISBN: | 9781523364022 |
Staff View
MARC
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| 300 | |a xxii, 311 Seiten |b Diagramme | ||
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| 337 | |b n |2 rdamedia | ||
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Record in the Search Index
| DE-BY-862_location | 2000 |
|---|---|
| DE-BY-FWS_call_number | 2000/ZN 4904 T455 |
| DE-BY-FWS_katkey | 709174 |
| DE-BY-FWS_media_number | 083000520944 |
| _version_ | 1824555693601980418 |
| any_adam_object | |
| author | Thomas, Donald B. |
| author_GND | (DE-588)1126511862 |
| author_facet | Thomas, Donald B. |
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| building | Verbundindex |
| bvnumber | BV045314197 |
| classification_rvk | ZN 4904 |
| ctrlnum | (OCoLC)1079408192 (DE-599)HEB381558932 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | Revised |
| format | Book |
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| id | DE-604.BV045314197 |
| illustrated | Not Illustrated |
| indexdate | 2025-02-20T07:11:43Z |
| institution | BVB |
| isbn | 9781523364022 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030701162 |
| oclc_num | 1079408192 |
| open_access_boolean | |
| owner | DE-862 DE-BY-FWS |
| owner_facet | DE-862 DE-BY-FWS |
| physical | xxii, 311 Seiten Diagramme |
| publishDate | 2016 |
| publishDateSearch | 2016 |
| publishDateSort | 2016 |
| publisher | Donald Thomas |
| record_format | marc |
| spellingShingle | Thomas, Donald B. Logic design and verification using SystemVerilog Digitalschaltung (DE-588)4012295-5 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd Hardwareverifikation (DE-588)4214982-4 gnd VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4012295-5 (DE-588)4159102-1 (DE-588)4214982-4 (DE-588)4268385-3 |
| title | Logic design and verification using SystemVerilog |
| title_auth | Logic design and verification using SystemVerilog |
| title_exact_search | Logic design and verification using SystemVerilog |
| title_full | Logic design and verification using SystemVerilog Donald Thomas |
| title_fullStr | Logic design and verification using SystemVerilog Donald Thomas |
| title_full_unstemmed | Logic design and verification using SystemVerilog Donald Thomas |
| title_short | Logic design and verification using SystemVerilog |
| title_sort | logic design and verification using systemverilog |
| topic | Digitalschaltung (DE-588)4012295-5 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd Hardwareverifikation (DE-588)4214982-4 gnd VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Digitalschaltung Hardwarebeschreibungssprache Hardwareverifikation VERILOG |
| work_keys_str_mv | AT thomasdonaldb logicdesignandverificationusingsystemverilog |
Sonderstandort Fakultät
| Call Number: |
2000 ZN 4904 T455 |
|---|---|
| Copy 1 | nicht ausleihbar Checked out – Due: 31.12.2099 Recall This |