Logic design and verification using SystemVerilog:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Pittsburgh, PA
Donald Thomas
[2016]
|
| Ausgabe: | Revised |
| Schlagworte: | |
| Beschreibung: | xxii, 311 Seiten Diagramme |
| ISBN: | 9781523364022 |
Internformat
MARC
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|---|---|---|---|
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| 003 | DE-604 | ||
| 005 | 20181217 | ||
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| 008 | 181127s2016 |||| |||| 00||| eng d | ||
| 020 | |a 9781523364022 |9 9781523364022 | ||
| 035 | |a (OCoLC)1079408192 | ||
| 035 | |a (DE-599)HEB381558932 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-862 | ||
| 084 | |a ZN 4904 |0 (DE-625)157419: |2 rvk | ||
| 100 | 1 | |a Thomas, Donald B. |e Verfasser |0 (DE-588)1126511862 |4 aut | |
| 245 | 1 | 0 | |a Logic design and verification using SystemVerilog |c Donald Thomas |
| 250 | |a Revised | ||
| 264 | 1 | |a Pittsburgh, PA |b Donald Thomas |c [2016] | |
| 264 | 3 | |a Lexington, KY |b CreateSpace | |
| 300 | |a xxii, 311 Seiten |b Diagramme | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a Digitalschaltung |0 (DE-588)4012295-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Hardwarebeschreibungssprache |0 (DE-588)4159102-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Hardwareverifikation |0 (DE-588)4214982-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Digitalschaltung |0 (DE-588)4012295-5 |D s |
| 689 | 0 | 1 | |a Hardwarebeschreibungssprache |0 (DE-588)4159102-1 |D s |
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| 689 | 0 | 3 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 0 | |5 DE-604 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030701162 | ||
Datensatz im Suchindex
| DE-BY-862_location | 2000 |
|---|---|
| DE-BY-FWS_call_number | 2000/ZN 4904 T455 |
| DE-BY-FWS_katkey | 709174 |
| DE-BY-FWS_media_number | 083000520944 |
| _version_ | 1824555693601980418 |
| any_adam_object | |
| author | Thomas, Donald B. |
| author_GND | (DE-588)1126511862 |
| author_facet | Thomas, Donald B. |
| author_role | aut |
| author_sort | Thomas, Donald B. |
| author_variant | d b t db dbt |
| building | Verbundindex |
| bvnumber | BV045314197 |
| classification_rvk | ZN 4904 |
| ctrlnum | (OCoLC)1079408192 (DE-599)HEB381558932 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | Revised |
| format | Book |
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| id | DE-604.BV045314197 |
| illustrated | Not Illustrated |
| indexdate | 2025-02-20T07:11:43Z |
| institution | BVB |
| isbn | 9781523364022 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030701162 |
| oclc_num | 1079408192 |
| open_access_boolean | |
| owner | DE-862 DE-BY-FWS |
| owner_facet | DE-862 DE-BY-FWS |
| physical | xxii, 311 Seiten Diagramme |
| publishDate | 2016 |
| publishDateSearch | 2016 |
| publishDateSort | 2016 |
| publisher | Donald Thomas |
| record_format | marc |
| spellingShingle | Thomas, Donald B. Logic design and verification using SystemVerilog Digitalschaltung (DE-588)4012295-5 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd Hardwareverifikation (DE-588)4214982-4 gnd VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4012295-5 (DE-588)4159102-1 (DE-588)4214982-4 (DE-588)4268385-3 |
| title | Logic design and verification using SystemVerilog |
| title_auth | Logic design and verification using SystemVerilog |
| title_exact_search | Logic design and verification using SystemVerilog |
| title_full | Logic design and verification using SystemVerilog Donald Thomas |
| title_fullStr | Logic design and verification using SystemVerilog Donald Thomas |
| title_full_unstemmed | Logic design and verification using SystemVerilog Donald Thomas |
| title_short | Logic design and verification using SystemVerilog |
| title_sort | logic design and verification using systemverilog |
| topic | Digitalschaltung (DE-588)4012295-5 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd Hardwareverifikation (DE-588)4214982-4 gnd VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Digitalschaltung Hardwarebeschreibungssprache Hardwareverifikation VERILOG |
| work_keys_str_mv | AT thomasdonaldb logicdesignandverificationusingsystemverilog |
Sonderstandort Fakultät
| Signatur: |
2000 ZN 4904 T455 |
|---|---|
| Exemplar 1 | nicht ausleihbar Checked out – Rückgabe bis: 31.12.2099 Vormerken |