Interconnect planning for physical design of 3D integrated circuits:
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis Book |
| Language: | English |
| Published: |
Düsseldorf
VDI-Verl.
2014
|
| Edition: | Als Ms. gedr. |
| Series: | Fortschritt-Berichte VDI
Reihe 20, Rechnerunterstützte Verfahren ; 455 |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Item Description: | Kurzfassung in dt. Sprache |
| Physical Description: | IX, 138 S. graph. Darst. |
| ISBN: | 9783183455201 |
Staff View
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| 246 | 1 | 3 | |a Interconnect planning for 3D-IC design |
| 250 | |a Als Ms. gedr. | ||
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Record in the Search Index
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|---|---|
| adam_text | CONTENTS
ABSTRACT VIII
KURZFASSUNG IX
1 INTRODUCTION 1
1.1 THE 3D INTEGRATION APPROACH FOR ELECTRONIC CIRCUITS 1
1.2 TECHNOLOGIES FOR 3D INTEGRATED CIRCUITS 6
1.3 DESIGN APPROACHES FOR 3D INTEGRATED CIRCUITS 8
2 STATE OF THE ART IN DESIGN AUTOMATION FOR 3D INTEGRATED
CIRCUITS 13
2.1 THERMAL MANAGEMENT 13
2.2 PARTITIONING AND FLOORPLANNING 14
2.3 PLACEMENT AND ROUTING 15
2.4 POWER AND CLOCK DELIVERY 16
2.5 DESIGN CHALLENGES 16
3 RESEARCH OBJECTIVES 18
4 PLANNING THROUGH-SILICON
VIA ISLANDS FOR BLOCK-LEVEL DESIGN REUSE 21
4.1 PROBLEMS FOR DESIGN REUSE IN 3D INTEGRATED CIRCUITS 21
4.2 CONNECTING BLOCKS USING THROUGH-SILICON VIA ISLANDS 23
4.2.1 PROBLEM FORMULATION AND METHODOLOGY OVERVIEW 25
4.2.2 NET CLUSTERING 26
4.2.3 INSERTION OF THROUGH-SILICON VIA ISLANDS 31
4.2.4 DEADSPACE INSERTION AND REDISTRIBUTION 34
4.3 EXPERIMENTAL INVESTIGATION 38
4.3.1 WIRELENGTH ESTIMATION 38
V
HTTP://D-NB.INFO/1055011153
CONTENTS
4.3.2 CONFIGURATION 39
4.3.3 RESULTS AND DISCUSSION 41
4.4 SUMMARY AND CONCLUSIONS 46
5 PLANNING THROUGH-SILICON VIAS
FOR DESIGN OPTIMIZATION 47
5.1 DEADSPACE REQUIREMENTS FOR OPTIMIZED PLANNING OF THROUGH-SILICON
VIAS 48
5.2 MULTIOBJECTIVE DESIGN OPTIMIZATION OF 3D INTEGRATED CIRCUITS 50
5.2.1 METHODOLOGY OVERVIEW AND CONFIGURATION 50
5.2.2 TECHNIQUES FOR DEADSPACE OPTIMIZATION 51
5.2.3 DESIGN-QUALITY ANALYSIS 55
5.2.4 PLANNING DIFFERENT TYPES OF THROUGH-SILICON WAS 55
5.3 EXPERIMENTAL INVESTIGATION 61
5.3.1 CONFIGURATION 61
5.3.2 RESULTS AND DISCUSSION 65
5.4 SUMMARY AND CONCLUSIONS 70
6 3D FLOORPLANNING FOR STRUCTURAL PLANNING
OF MASSIVE INTERCONNECTS 71
6.1 BLOCK ALIGNMENT FOR INTERCONNECTS PLANNING IN 3D INTEGRATED CIRCUITS
. . . 72
6.2 CORNER BLOCK LIST EXTENDED FOR BLOCK ALIGNMENT 74
6.2.1 ALIGNMENT ENCODING 75
6.2.2 LAYOUT GENERATION: BLOCK PLACEMENT AND ALIGNMENT 78
6.3 3D FLOORPLANNING METHODOLOGY 85
6.3.1 OPTIMIZATION CRITERIA AND PHASES AND RELATED COST MODELS 85
6.3.2 FAST THERMAL ANALYSIS 88
6.3.3 LAYOUT OPERATIONS 90
6.3.4 ADAPTIVE OPTIMIZATION SCHEDULE 91
6.4 EXPERIMENTAL INVESTIGATION 92
6.4.1 CONFIGURATION 93
6.4.2 RESULTS AND DISCUSSION 94
6.5 SUMMARY AND CONCLUSIONS 99
7 RESEARCH SUMMARY, CONCLUSIONS, AND OUTLOOK 101
DISSERTATION THESES 107
VI
NOTATION
GLOSSARY
BIBLIOGRAPHY
CONTENTS
110
116
121
VII
|
| any_adam_object | 1 |
| author | Knechtel, Johann |
| author_facet | Knechtel, Johann |
| author_role | aut |
| author_sort | Knechtel, Johann |
| author_variant | j k jk |
| building | Verbundindex |
| bvnumber | BV042014328 |
| classification_rvk | ZN 4192 ZN 4904 |
| classification_tum | ELT 340d |
| ctrlnum | (OCoLC)889445862 (DE-599)GBV790401053 |
| dewey-full | 621.3 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3 |
| dewey-search | 621.3 |
| dewey-sort | 3621.3 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | Als Ms. gedr. |
| format | Thesis Book |
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| genre_facet | Hochschulschrift |
| id | DE-604.BV042014328 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T01:10:33Z |
| institution | BVB |
| isbn | 9783183455201 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-027456153 |
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| physical | IX, 138 S. graph. Darst. |
| publishDate | 2014 |
| publishDateSearch | 2014 |
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| publisher | VDI-Verl. |
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| series | Fortschritt-Berichte VDI |
| series2 | Fortschritt-Berichte VDI : Reihe 20, Rechnerunterstützte Verfahren |
| spelling | Knechtel, Johann Verfasser aut Interconnect planning for physical design of 3D integrated circuits Johann Knechtel Interconnect planning for 3D-IC design Als Ms. gedr. Düsseldorf VDI-Verl. 2014 IX, 138 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Fortschritt-Berichte VDI : Reihe 20, Rechnerunterstützte Verfahren 455 Kurzfassung in dt. Sprache Zugl.: Dresden, Techn. Univ., Diss., 2014 Silicium (DE-588)4077445-4 gnd rswk-swf Block-Layout (DE-588)4264877-4 gnd rswk-swf Layout Mikroelektronik (DE-588)4264372-7 gnd rswk-swf Durchkontaktieren (DE-588)4150891-9 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf Dreidimensionale Integration (DE-588)4218841-6 gnd rswk-swf Verbindungstechnik (DE-588)4129183-9 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Dreidimensionale Integration (DE-588)4218841-6 s Layout Mikroelektronik (DE-588)4264372-7 s Block-Layout (DE-588)4264877-4 s Durchkontaktieren (DE-588)4150891-9 s Silicium (DE-588)4077445-4 s Verbindungstechnik (DE-588)4129183-9 s Entwurfsautomation (DE-588)4312536-0 s VLSI (DE-588)4117388-0 s DE-604 Fortschritt-Berichte VDI Reihe 20, Rechnerunterstützte Verfahren ; 455 (DE-604)BV021786833 455 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027456153&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Knechtel, Johann Interconnect planning for physical design of 3D integrated circuits Fortschritt-Berichte VDI Silicium (DE-588)4077445-4 gnd Block-Layout (DE-588)4264877-4 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd Durchkontaktieren (DE-588)4150891-9 gnd VLSI (DE-588)4117388-0 gnd Entwurfsautomation (DE-588)4312536-0 gnd Dreidimensionale Integration (DE-588)4218841-6 gnd Verbindungstechnik (DE-588)4129183-9 gnd |
| subject_GND | (DE-588)4077445-4 (DE-588)4264877-4 (DE-588)4264372-7 (DE-588)4150891-9 (DE-588)4117388-0 (DE-588)4312536-0 (DE-588)4218841-6 (DE-588)4129183-9 (DE-588)4113937-9 |
| title | Interconnect planning for physical design of 3D integrated circuits |
| title_alt | Interconnect planning for 3D-IC design |
| title_auth | Interconnect planning for physical design of 3D integrated circuits |
| title_exact_search | Interconnect planning for physical design of 3D integrated circuits |
| title_full | Interconnect planning for physical design of 3D integrated circuits Johann Knechtel |
| title_fullStr | Interconnect planning for physical design of 3D integrated circuits Johann Knechtel |
| title_full_unstemmed | Interconnect planning for physical design of 3D integrated circuits Johann Knechtel |
| title_short | Interconnect planning for physical design of 3D integrated circuits |
| title_sort | interconnect planning for physical design of 3d integrated circuits |
| topic | Silicium (DE-588)4077445-4 gnd Block-Layout (DE-588)4264877-4 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd Durchkontaktieren (DE-588)4150891-9 gnd VLSI (DE-588)4117388-0 gnd Entwurfsautomation (DE-588)4312536-0 gnd Dreidimensionale Integration (DE-588)4218841-6 gnd Verbindungstechnik (DE-588)4129183-9 gnd |
| topic_facet | Silicium Block-Layout Layout Mikroelektronik Durchkontaktieren VLSI Entwurfsautomation Dreidimensionale Integration Verbindungstechnik Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027456153&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV021786833 |
| work_keys_str_mv | AT knechteljohann interconnectplanningforphysicaldesignof3dintegratedcircuits AT knechteljohann interconnectplanningfor3dicdesign |