SystemVerilog for verification: a guide to learning the testbench language features
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| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
New York, NY
Springer
2008
|
| Edition: | 2. ed. |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Item Description: | Literaturverz. S. [421] - 422 |
| Physical Description: | XXXVI, 429 S. Ill., graph. Darst. 235 mm x 155 mm |
| ISBN: | 9780387765297 0387765298 |
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| 245 | 1 | 0 | |a SystemVerilog for verification |b a guide to learning the testbench language features |c Chris Spear |
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| 264 | 1 | |a New York, NY |b Springer |c 2008 | |
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Record in the Search Index
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| adam_text | CHRIS SPEAR SYSTEMVERILOG FOR VERIFICATION A GUIDE TO LEARNING THE
TESTBENCH LANGUAGE FEATURES SECOND EDITION SPRINGER CONTENTS LISTOF
EXAMP] LISTOF FIGURES LISTOF TABLES PREFACE LES ACKNOWLEDGMENTS 1.
VERIFICATION GUIDELINES 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11
1.12 1.13 1.14 1.15 THE VERIFICATION PROCESS THE VERIFICATION
METHODOLOGY MANUAL BASIC TESTBENCH FUNCTIONALITY DIRECTED TESTING
METHODOLOGY BASICS CONSTRAINED-RANDOM STIMULUS WHAT SHOULD YOU
RANDOMIZE? FUNCTIONAL COVERAGE TESTBENCH COMPONENTS LAYERED TESTBENCH
BUILDING A LAYERED TESTBENCH SIMULATION ENVIRONMENT PHASES MAXIMUM CODE
REUSE TESTBENCH PERFORMANCE CONCLUSION XLLL XXV XXVII XXIX XXXV 1 2 4 5
5 7 8 10 13 14 15 21 22 23 23 24 2. DATA TYPES 25 2.1 BUILT-IN DATA
TYPES 25 2.2 FIXED-SIZE ARRAYS 28 2.3 DYNAMIC ARRAYS 34 2.4 QUEUES 36
2.5 ASSOCIATIVE ARRAYS 38 VLLL CONTENTS 40 41 46 48 50 52 55 59 59 60 61
63 63 65 65 66 72 73 75 77 4. CONNECTING THE TESTBENCH AND DESIGN 79 4.1
SEPARATING THE TESTBENCH AND DESIGN 80 4.2 THE INTERFACE CONSTRUCT 82
4.3 STIMULUS TIMING 88 4.4 INTERFACE DRIVING AND SAMPLING 96 4.5
CONNECTING IT ALL TOGETHER 103 4.6 TOP-LEVEL SCOPE 104 4.7 PROGRAM -
MODULE INTERACTIONS 106 4.8 SYSTEM VERILOG ASSERTIONS 107 4.9 THE
FOUR-PORT ATM ROUTER 109 4.10 THE REF PORT DIRECTION 117 4.11 THE ENDOF
SIMULATION 118 4.12 DIRECTED TEST FOR THE LC3 FETCH BLOCK 118 4.13
CONCLUSION 124 5. BASIC OOP 125 5.1 INTRODUCTION 125 5.2 THINK OFNOUNS,
NOT VERBS 126 5.3 YOUR FIRST CLASS 126 2.6 2.7 2.8 2.9 2.10 2.11 2.12
2.13 2.14 2.15 2.16 LINKED LISTS ARRAY METHODS CHOOSING A STORAGE TYPE
CREATING NEW TYPES WITH TYPEDEF CREATING USER-DEFMED STRUCTURES TYPE
CONVERSION ENUMERATED TYPES CONSTANTS STRINGS EXPRESSION WIDTH
CONCLUSION PROCEDURAL STATEMENTS AND ROUTINES 3.1 3.2 3.3 3.4 3.5 3.6
3.7 3.8 PROCEDURAL STATEMENTS TASKS, FUNCTIONS, AND VOID FUNCTIONS TASK
AND FUNCTION OVERVIEW ROUTINE ARGUMENTS RETURNING FROM A ROUTINE LOCAL
DATA STORAGE TIME VALUES CONCLUSION CONTENTS IX 6. 5.4 5.5 5.6 5.7 5.8
5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 NDO 6.1 6.2 6.3
6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18
IEA] 7.1 7.2 7.3 7.4 7.5 7.6 WHERE TO DEFINE A CLASS OOP TERMINOLOGY
CREATING NEW OBJECTS OBJECT DEALLOCATION USING OBJECTS STATIC VARIABLES
VS. GLOBAL VARIABLES CLASS METHODS DEFINING METHODS OUTSIDE OF THE CLASS
SCOPING RULES USING ONE CLASS INSIDE ANOTHER UNDERSTANDING DYNAMIC
OBJECTS COPYING OBJECTS PUBLIC VS. LOCAL STRAYING OFFCOURSE BUILDING A
TESTBENCH CONCLUSION MIZATION INTRODUCTION WHAT TO RANDOMIZE
RANDOMIZATION IN SYSTEM VERFLOG CONSTRAINT DETAILS SOLUTION
PROBABILITIES CONTROLLING MULTIPLE CONSTRAINT BLOCKS VALID CONSTRAINTS
IN-LINE CONSTRAINTS THE PRERANDOMIZE AND POST_RANDOMIZE FUNCTIONS RANDOM
NUMBER FUNCTIONS CONSTRAINTS TIPS AND TECHNIQUES COMMON RANDOMIZATION
PROBLEMS ITERATIVE AND ARRAY CONSTRAINTS ATOMIC STIMULUS GENERATION VS.
SCENARIO GENERATION RANDOM CONTROL RANDOM NUMBER GENERATORS RANDOM
DEVICE CONFIGURATION CONCLUSION DS AND INTERPROCESS COMMUNICATION
WORKING WITH THREADS DISABLING THREADS INTERPROCESS COMMUNICATION EVENTS
SEMAPHORES MAILBOXES 127 128 129 132 134 134 138 139 141 144 147 151 157
157 158 159 161 161 162 165 167 178 182 183 184 185 187 187 193 195 204
207 209 213 216 217 218 228 232 233 238 240 CONTENTS 1.1 BUILDING A
TESTBENCH WITH THREADS AND IPC 253 7.8 CONCLUSION 257 ADVANCED OOP AND
TESTBENCH GUIDELINES 259 8.1 INTRODUCTION TO INHERITANCE 260 8.2
BLUEPRINT PATTERN 265 8.3 DOWNCASTING AND VIRTUAL METHODS 270 8.4
COMPOSITION, INHERITANCE, AND ALTERNATIVES 274 8.5 COPYING AN OBJECT 279
8.6 ABSTRACT CLASSES AND PURE VIRTUAL METHODS 282 8.7 CALLBACKS 284 8.8
PARAMETERIZED CLASSES 290 8.9 CONCLUSION 293 FUNCTIONAL COVERAGE 295 9.1
COVERAGE TYPES 298 9.2 FUNCTIONAL COVERAGE STRATEGIES 301 9.3 SIMPLE
FUNCTIONAL COVERAGE EXAMPLE 303 9.4 ANATOMYOFA COVER GROUP 305 9.5
TRIGGERING A COVER GROUP 307 9.6 DATASAMPLING 310 9.7 CROSS COVERAGE 319
9.8 GENERIC COVER GROUPS 325 9.9 COVERAGE OPTIONS 327 9.10 ANALYZING
COVERAGE DATA 329 9.11 MEASURING COVERAGE STATISTICS DURING SIMULATION
331 9.12 CONCLUSION 332 ADVANCED INTERFACES 333 10.1 VIRTUAL INTERFACES
WITH THE ATM ROUTER 334 10.2 CONNECTING TO MULTIPLE DESIGN
CONFIGURATIONS 342 10.3 PROCEDURAL CODE IN AN INTERFACE 347 10.4
CONCLUSION 350 A COMPLETE SYSTEMVERILOG TESTBENCH 351 11.1 DESIGN BLOCKS
351 11.2 TESTBENCH BLOCKS 356 11.3 ALTERNATE TESTS 377 11.4 CONCLUSION
379 INTERF ACING WITH C 381 12.1 PASSING SIMPLE VALUES 382 CONTENTS XI
12.2 CONNECTING TO A SIMPLE C ROUTINE 12.3 CONNECTING TO C++ 12.4 SIMPLE
ARRAY SHARING 12.5 OPEN ARRAYS 12.6 SHARING COMPOSITE TYPES 12.7 PURE
AND CONTEXT IMPORTED METHODS 12.8 COMMUNICATING FROM C TO SYSTEM VERILOG
12.9 CONNECTING OTHER LANGUAGES 12.10 CONCLUSION 385 393 398 400 404 407
407 418 419 REFERENCES INDEX 421 423
|
| adam_txt |
CHRIS SPEAR SYSTEMVERILOG FOR VERIFICATION A GUIDE TO LEARNING THE
TESTBENCH LANGUAGE FEATURES SECOND EDITION SPRINGER CONTENTS LISTOF
EXAMP] LISTOF FIGURES LISTOF TABLES PREFACE LES ACKNOWLEDGMENTS 1.
VERIFICATION GUIDELINES 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11
1.12 1.13 1.14 1.15 THE VERIFICATION PROCESS THE VERIFICATION
METHODOLOGY MANUAL BASIC TESTBENCH FUNCTIONALITY DIRECTED TESTING
METHODOLOGY BASICS CONSTRAINED-RANDOM STIMULUS WHAT SHOULD YOU
RANDOMIZE? FUNCTIONAL COVERAGE TESTBENCH COMPONENTS LAYERED TESTBENCH
BUILDING A LAYERED TESTBENCH SIMULATION ENVIRONMENT PHASES MAXIMUM CODE
REUSE TESTBENCH PERFORMANCE CONCLUSION XLLL XXV XXVII XXIX XXXV 1 2 4 5
5 7 8 10 13 14 15 21 22 23 23 24 2. DATA TYPES 25 2.1 BUILT-IN DATA
TYPES 25 2.2 FIXED-SIZE ARRAYS 28 2.3 DYNAMIC ARRAYS 34 2.4 QUEUES 36
2.5 ASSOCIATIVE ARRAYS 38 VLLL CONTENTS 40 41 46 48 50 52 55 59 59 60 61
63 63 65 65 66 72 73 75 77 4. CONNECTING THE TESTBENCH AND DESIGN 79 4.1
SEPARATING THE TESTBENCH AND DESIGN 80 4.2 THE INTERFACE CONSTRUCT 82
4.3 STIMULUS TIMING 88 4.4 INTERFACE DRIVING AND SAMPLING 96 4.5
CONNECTING IT ALL TOGETHER 103 4.6 TOP-LEVEL SCOPE 104 4.7 PROGRAM -
MODULE INTERACTIONS 106 4.8 SYSTEM VERILOG ASSERTIONS 107 4.9 THE
FOUR-PORT ATM ROUTER 109 4.10 THE REF PORT DIRECTION 117 4.11 THE ENDOF
SIMULATION 118 4.12 DIRECTED TEST FOR THE LC3 FETCH BLOCK 118 4.13
CONCLUSION 124 5. BASIC OOP 125 5.1 INTRODUCTION 125 5.2 THINK OFNOUNS,
NOT VERBS 126 5.3 YOUR FIRST CLASS 126 2.6 2.7 2.8 2.9 2.10 2.11 2.12
2.13 2.14 2.15 2.16 LINKED LISTS ARRAY METHODS CHOOSING A STORAGE TYPE
CREATING NEW TYPES WITH TYPEDEF CREATING USER-DEFMED STRUCTURES TYPE
CONVERSION ENUMERATED TYPES CONSTANTS STRINGS EXPRESSION WIDTH
CONCLUSION PROCEDURAL STATEMENTS AND ROUTINES 3.1 3.2 3.3 3.4 3.5 3.6
3.7 3.8 PROCEDURAL STATEMENTS TASKS, FUNCTIONS, AND VOID FUNCTIONS TASK
AND FUNCTION OVERVIEW ROUTINE ARGUMENTS RETURNING FROM A ROUTINE LOCAL
DATA STORAGE TIME VALUES CONCLUSION CONTENTS IX 6. 5.4 5.5 5.6 5.7 5.8
5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 NDO 6.1 6.2 6.3
6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18
IEA] 7.1 7.2 7.3 7.4 7.5 7.6 WHERE TO DEFINE A CLASS OOP TERMINOLOGY
CREATING NEW OBJECTS OBJECT DEALLOCATION USING OBJECTS STATIC VARIABLES
VS. GLOBAL VARIABLES CLASS METHODS DEFINING METHODS OUTSIDE OF THE CLASS
SCOPING RULES USING ONE CLASS INSIDE ANOTHER UNDERSTANDING DYNAMIC
OBJECTS COPYING OBJECTS PUBLIC VS. LOCAL STRAYING OFFCOURSE BUILDING A
TESTBENCH CONCLUSION MIZATION INTRODUCTION WHAT TO RANDOMIZE
RANDOMIZATION IN SYSTEM VERFLOG CONSTRAINT DETAILS SOLUTION
PROBABILITIES CONTROLLING MULTIPLE CONSTRAINT BLOCKS VALID CONSTRAINTS
IN-LINE CONSTRAINTS THE PRERANDOMIZE AND POST_RANDOMIZE FUNCTIONS RANDOM
NUMBER FUNCTIONS CONSTRAINTS TIPS AND TECHNIQUES COMMON RANDOMIZATION
PROBLEMS ITERATIVE AND ARRAY CONSTRAINTS ATOMIC STIMULUS GENERATION VS.
SCENARIO GENERATION RANDOM CONTROL RANDOM NUMBER GENERATORS RANDOM
DEVICE CONFIGURATION CONCLUSION DS AND INTERPROCESS COMMUNICATION
WORKING WITH THREADS DISABLING THREADS INTERPROCESS COMMUNICATION EVENTS
SEMAPHORES MAILBOXES 127 128 129 132 134 134 138 139 141 144 147 151 157
157 158 159 161 161 162 165 167 178 182 183 184 185 187 187 193 195 204
207 209 213 216 217 218 228 232 233 238 240 CONTENTS 1.1 BUILDING A
TESTBENCH WITH THREADS AND IPC 253 7.8 CONCLUSION 257 ADVANCED OOP AND
TESTBENCH GUIDELINES 259 8.1 INTRODUCTION TO INHERITANCE 260 8.2
BLUEPRINT PATTERN 265 8.3 DOWNCASTING AND VIRTUAL METHODS 270 8.4
COMPOSITION, INHERITANCE, AND ALTERNATIVES 274 8.5 COPYING AN OBJECT 279
8.6 ABSTRACT CLASSES AND PURE VIRTUAL METHODS 282 8.7 CALLBACKS 284 8.8
PARAMETERIZED CLASSES 290 8.9 CONCLUSION 293 FUNCTIONAL COVERAGE 295 9.1
COVERAGE TYPES 298 9.2 FUNCTIONAL COVERAGE STRATEGIES 301 9.3 SIMPLE
FUNCTIONAL COVERAGE EXAMPLE 303 9.4 ANATOMYOFA COVER GROUP 305 9.5
TRIGGERING A COVER GROUP 307 9.6 DATASAMPLING 310 9.7 CROSS COVERAGE 319
9.8 GENERIC COVER GROUPS 325 9.9 COVERAGE OPTIONS 327 9.10 ANALYZING
COVERAGE DATA 329 9.11 MEASURING COVERAGE STATISTICS DURING SIMULATION
331 9.12 CONCLUSION 332 ADVANCED INTERFACES 333 10.1 VIRTUAL INTERFACES
WITH THE ATM ROUTER 334 10.2 CONNECTING TO MULTIPLE DESIGN
CONFIGURATIONS 342 10.3 PROCEDURAL CODE IN AN INTERFACE 347 10.4
CONCLUSION 350 A COMPLETE SYSTEMVERILOG TESTBENCH 351 11.1 DESIGN BLOCKS
351 11.2 TESTBENCH BLOCKS 356 11.3 ALTERNATE TESTS 377 11.4 CONCLUSION
379 INTERF ACING WITH C 381 12.1 PASSING SIMPLE VALUES 382 CONTENTS XI
12.2 CONNECTING TO A SIMPLE C ROUTINE 12.3 CONNECTING TO C++ 12.4 SIMPLE
ARRAY SHARING 12.5 OPEN ARRAYS 12.6 SHARING COMPOSITE TYPES 12.7 PURE
AND CONTEXT IMPORTED METHODS 12.8 COMMUNICATING FROM C TO SYSTEM VERILOG
12.9 CONNECTING OTHER LANGUAGES 12.10 CONCLUSION 385 393 398 400 404 407
407 418 419 REFERENCES INDEX 421 423 |
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| id | DE-604.BV035027078 |
| illustrated | Illustrated |
| index_date | 2024-07-02T21:48:24Z |
| indexdate | 2024-07-09T21:20:31Z |
| institution | BVB |
| isbn | 9780387765297 0387765298 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-016696115 |
| oclc_num | 254591847 |
| open_access_boolean | |
| owner | DE-92 |
| owner_facet | DE-92 |
| physical | XXXVI, 429 S. Ill., graph. Darst. 235 mm x 155 mm |
| publishDate | 2008 |
| publishDateSearch | 2008 |
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| publisher | Springer |
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| spelling | Spear, Chris Verfasser aut SystemVerilog for verification a guide to learning the testbench language features Chris Spear 2. ed. New York, NY Springer 2008 XXXVI, 429 S. Ill., graph. Darst. 235 mm x 155 mm txt rdacontent n rdamedia nc rdacarrier Literaturverz. S. [421] - 422 Integrated circuits Verification Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd rswk-swf VERILOG (DE-588)4268385-3 s DE-604 GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016696115&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Spear, Chris SystemVerilog for verification a guide to learning the testbench language features Integrated circuits Verification Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4268385-3 |
| title | SystemVerilog for verification a guide to learning the testbench language features |
| title_auth | SystemVerilog for verification a guide to learning the testbench language features |
| title_exact_search | SystemVerilog for verification a guide to learning the testbench language features |
| title_exact_search_txtP | SystemVerilog for verification a guide to learning the testbench language features |
| title_full | SystemVerilog for verification a guide to learning the testbench language features Chris Spear |
| title_fullStr | SystemVerilog for verification a guide to learning the testbench language features Chris Spear |
| title_full_unstemmed | SystemVerilog for verification a guide to learning the testbench language features Chris Spear |
| title_short | SystemVerilog for verification |
| title_sort | systemverilog for verification a guide to learning the testbench language features |
| title_sub | a guide to learning the testbench language features |
| topic | Integrated circuits Verification Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Integrated circuits Verification Verilog (Computer hardware description language) VERILOG |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016696115&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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