Advances in 3D integrated circuits and systems /:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Weitere Verfasser: | |
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
New Jersey :
World Scientific,
2015.
|
| Schriftenreihe: | Series on emerging technologies in circuits and systems ;
vol. 1. |
| Schlagworte: | |
| Online-Zugang: | DE-862 DE-863 |
| Beschreibung: | 1 online resource |
| Bibliographie: | Includes bibliographical references and index. |
| ISBN: | 9789814699020 9814699020 |
Internformat
MARC
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| 100 | 1 | |a Yu, Hao |c (Electrical engineer), |e author. |1 https://id.oclc.org/worldcat/entity/E39PCjvFy3PxKdYtBcdhgJtWTb |0 http://id.loc.gov/authorities/names/n2015034167 | |
| 245 | 1 | 0 | |a Advances in 3D integrated circuits and systems / |c by Hao Yu (NTU, Singapore), Chuan-Seng Tan (NTU, Singapore). |
| 264 | 1 | |a New Jersey : |b World Scientific, |c 2015. | |
| 264 | 4 | |c ©2016 | |
| 300 | |a 1 online resource | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
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| 490 | 1 | |a Series on emerging technologies in circuits and systems | |
| 504 | |a Includes bibliographical references and index. | ||
| 588 | 0 | |a Print version record. | |
| 505 | 0 | |a Preface; 1. Introduction; 1.1 Thousand-core On-chip; 1.2 State-of-the-Art Many-core Microprocessors; 1.3 Memory-logic Integration; 1.3.1 2D Integration Challenges; 1.3.1.1 Scalability; 1.3.1.2 Channel Loss; 1.3.1.3 I/O Circuit Design; 1.3.1.4 Testing; 1.3.1.5 Thermal Management; 1.3.1.6 Power Management; 1.3.1.7 I/OManagement; 1.3.2 3D Integration; 1.3.3 2.5D Integration; 1.4 Organization of the Book; Part 1. Device Modeling; 2. Fabrication; 2.1 Introduction; 2.2 TSV Structure and Fabrication; 2.2.1 Structure Design; 2.2.1.1 Wafer Layout and Mask Design. | |
| 505 | 8 | |a 2.2.1.2 Electrical Structure Design2.2.1.3 Thermal Structure Design; 2.2.1.4 Dummy TSV Blocks; 2.2.2 Fabrication Process; 2.2.2.1 Electrical Structure Fabrication Process; 2.2.2.2 Thermal Structure Fabrication Process; 2.2.3 Process Control and Optimization; 2.2.3.1 DRIE Si Etch; 2.2.3.2 Dielectric Liner Deposition; 2.2.3.3 Ta Barrier/Cu Seed Layer Deposition and Cu ECP; 2.2.3.4 Cu CMP; 2.3 TSV Electrical Characterization; 2.3.1 Measurement Setup; 2.3.2 Conventional PETEOS Oxide Liner; 2.3.2.1 Electrical CV Measurement; 2.3.2.2 Electrical IV Measurement; 2.3.3 Black Diamond Low-k Liner. | |
| 505 | 8 | |a 2.3.3.1 Electrical CV Measurement2.3.3.2 Electrical IV Measurement; 2.3.4 Al2O3/Oxide Bi-layer Liner; 2.3.4.1 Electrical CV Measurement; 2.3.4.2 Electrical IV Measurement; 2.4 TSV Thermal Characterization Results; 2.4.1 Measurement Setup; 2.4.2 Cu-TSV Thermal Modeling; 2.4.3 Cu-TSV Induced Stress Modeling; 2.4.4 Cu-TSV Induced Stress Measurement by Micro-Raman Analysis; 2.5 TSI Structure and Fabrication; 2.5.1 Structure Design; 2.5.2 Fabrication Process; 2.6 Summary; 3. Device Model; 3.1 Introduction; 3.2 Nonlinear MOSCAP Model; 3.3 TSV Device Model; 3.3.1 Electrical Model. | |
| 505 | 8 | |a 3.3.2 Thermal Model3.3.3 Mechanical Model; 3.3.4 Delay Model; 3.3.4.1 Electrical-Thermal Coupled Delay Model; 3.3.4.2 Electrical-Mechanical Coupled Delay Model ; 3.3.4.3 Electrical-Thermal-Mechanical Coupled Delay Model; 3.3.5 Power Model; 3.4 TSI Device Model; 3.4.1 Delay Model; 3.4.1.1 T-line Model; 3.4.1.2 Delay of T-line; 3.4.2 Power Model; 3.4.2.1 TSV and TSI Comparison; 3.4.2.2 Energy-efficiency Analysis; 3.5 Summary; Part 2. Physical Design; 4. Macromodel; 4.1 Introduction; 4.2 Power and Thermal Integrity; 4.3 Macromodeling; 4.3.1 Complexity Compression. | |
| 505 | 8 | |a 4.3.1.1 Complexity Compression of States4.3.1.2 Complexity Compression of I/Os; 4.3.2 Parameterization; 4.4 Summary; 5. TSV Allocation; 5.1 Introduction; 5.2 Power Ground Design; 5.2.1 Problem Formulation; 5.2.2 Sensitivity based TSV Allocation; 5.3 Clock-treeDesign; 5.3.1 ProblemFormulation; 5.3.2 Sensitivity based TSV Allocation; 5.3.2.1 Reduction of Thermal Gradient; 5.3.2.2 Reduction of Stress Gradient; 5.3.2.3 Clock-skew Reduction; 5.4 Summary; 6. Testing; 6.1 Introduction; 6.2 3D IC Test; 6.2.1 System Architecture; 6.2.2 Problem Formulation. | |
| 650 | 0 | |a Three-dimensional integrated circuits. |0 http://id.loc.gov/authorities/subjects/sh2011002115 | |
| 650 | 6 | |a Circuits intégrés tridimensionnels. | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Mechanical. |2 bisacsh | |
| 650 | 7 | |a Three-dimensional integrated circuits |2 fast | |
| 700 | 1 | |a Tan, Chuan Seng. | |
| 758 | |i has work: |a Advances in 3D integrated circuits and systems (Text) |1 https://id.oclc.org/worldcat/entity/E39PCGcgr7PtyKKHVGwccGT9rC |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
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| 830 | 0 | |a Series on emerging technologies in circuits and systems ; |v vol. 1. |0 http://id.loc.gov/authorities/names/no2017022094 | |
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Datensatz im Suchindex
| DE-BY-FWS_katkey | ZDB-4-EBA-ocn922922497 |
|---|---|
| _version_ | 1826942093763805184 |
| adam_text | |
| any_adam_object | |
| author | Yu, Hao (Electrical engineer) |
| author2 | Tan, Chuan Seng |
| author2_role | |
| author2_variant | c s t cs cst |
| author_GND | http://id.loc.gov/authorities/names/n2015034167 |
| author_facet | Yu, Hao (Electrical engineer) Tan, Chuan Seng |
| author_role | aut |
| author_sort | Yu, Hao (Electrical engineer) |
| author_variant | h y hy |
| building | Verbundindex |
| bvnumber | localFWS |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874.893 .Y83 2015 |
| callnumber-search | TK7874.893 .Y83 2015 |
| callnumber-sort | TK 47874.893 Y83 42015 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| collection | ZDB-4-EBA |
| contents | Preface; 1. Introduction; 1.1 Thousand-core On-chip; 1.2 State-of-the-Art Many-core Microprocessors; 1.3 Memory-logic Integration; 1.3.1 2D Integration Challenges; 1.3.1.1 Scalability; 1.3.1.2 Channel Loss; 1.3.1.3 I/O Circuit Design; 1.3.1.4 Testing; 1.3.1.5 Thermal Management; 1.3.1.6 Power Management; 1.3.1.7 I/OManagement; 1.3.2 3D Integration; 1.3.3 2.5D Integration; 1.4 Organization of the Book; Part 1. Device Modeling; 2. Fabrication; 2.1 Introduction; 2.2 TSV Structure and Fabrication; 2.2.1 Structure Design; 2.2.1.1 Wafer Layout and Mask Design. 2.2.1.2 Electrical Structure Design2.2.1.3 Thermal Structure Design; 2.2.1.4 Dummy TSV Blocks; 2.2.2 Fabrication Process; 2.2.2.1 Electrical Structure Fabrication Process; 2.2.2.2 Thermal Structure Fabrication Process; 2.2.3 Process Control and Optimization; 2.2.3.1 DRIE Si Etch; 2.2.3.2 Dielectric Liner Deposition; 2.2.3.3 Ta Barrier/Cu Seed Layer Deposition and Cu ECP; 2.2.3.4 Cu CMP; 2.3 TSV Electrical Characterization; 2.3.1 Measurement Setup; 2.3.2 Conventional PETEOS Oxide Liner; 2.3.2.1 Electrical CV Measurement; 2.3.2.2 Electrical IV Measurement; 2.3.3 Black Diamond Low-k Liner. 2.3.3.1 Electrical CV Measurement2.3.3.2 Electrical IV Measurement; 2.3.4 Al2O3/Oxide Bi-layer Liner; 2.3.4.1 Electrical CV Measurement; 2.3.4.2 Electrical IV Measurement; 2.4 TSV Thermal Characterization Results; 2.4.1 Measurement Setup; 2.4.2 Cu-TSV Thermal Modeling; 2.4.3 Cu-TSV Induced Stress Modeling; 2.4.4 Cu-TSV Induced Stress Measurement by Micro-Raman Analysis; 2.5 TSI Structure and Fabrication; 2.5.1 Structure Design; 2.5.2 Fabrication Process; 2.6 Summary; 3. Device Model; 3.1 Introduction; 3.2 Nonlinear MOSCAP Model; 3.3 TSV Device Model; 3.3.1 Electrical Model. 3.3.2 Thermal Model3.3.3 Mechanical Model; 3.3.4 Delay Model; 3.3.4.1 Electrical-Thermal Coupled Delay Model; 3.3.4.2 Electrical-Mechanical Coupled Delay Model ; 3.3.4.3 Electrical-Thermal-Mechanical Coupled Delay Model; 3.3.5 Power Model; 3.4 TSI Device Model; 3.4.1 Delay Model; 3.4.1.1 T-line Model; 3.4.1.2 Delay of T-line; 3.4.2 Power Model; 3.4.2.1 TSV and TSI Comparison; 3.4.2.2 Energy-efficiency Analysis; 3.5 Summary; Part 2. Physical Design; 4. Macromodel; 4.1 Introduction; 4.2 Power and Thermal Integrity; 4.3 Macromodeling; 4.3.1 Complexity Compression. 4.3.1.1 Complexity Compression of States4.3.1.2 Complexity Compression of I/Os; 4.3.2 Parameterization; 4.4 Summary; 5. TSV Allocation; 5.1 Introduction; 5.2 Power Ground Design; 5.2.1 Problem Formulation; 5.2.2 Sensitivity based TSV Allocation; 5.3 Clock-treeDesign; 5.3.1 ProblemFormulation; 5.3.2 Sensitivity based TSV Allocation; 5.3.2.1 Reduction of Thermal Gradient; 5.3.2.2 Reduction of Stress Gradient; 5.3.2.3 Clock-skew Reduction; 5.4 Summary; 6. Testing; 6.1 Introduction; 6.2 3D IC Test; 6.2.1 System Architecture; 6.2.2 Problem Formulation. |
| ctrlnum | (OCoLC)922922497 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | ZDB-4-EBA-ocn922922497 |
| illustrated | Not Illustrated |
| indexdate | 2025-03-18T14:22:32Z |
| institution | BVB |
| isbn | 9789814699020 9814699020 |
| language | English |
| oclc_num | 922922497 |
| open_access_boolean | |
| owner | MAIN DE-862 DE-BY-FWS DE-863 DE-BY-FWS |
| owner_facet | MAIN DE-862 DE-BY-FWS DE-863 DE-BY-FWS |
| physical | 1 online resource |
| psigel | ZDB-4-EBA FWS_PDA_EBA ZDB-4-EBA |
| publishDate | 2015 |
| publishDateSearch | 2015 |
| publishDateSort | 2015 |
| publisher | World Scientific, |
| record_format | marc |
| series | Series on emerging technologies in circuits and systems ; |
| series2 | Series on emerging technologies in circuits and systems |
| spelling | Yu, Hao (Electrical engineer), author. https://id.oclc.org/worldcat/entity/E39PCjvFy3PxKdYtBcdhgJtWTb http://id.loc.gov/authorities/names/n2015034167 Advances in 3D integrated circuits and systems / by Hao Yu (NTU, Singapore), Chuan-Seng Tan (NTU, Singapore). New Jersey : World Scientific, 2015. ©2016 1 online resource text txt rdacontent computer c rdamedia online resource cr rdacarrier Series on emerging technologies in circuits and systems Includes bibliographical references and index. Print version record. Preface; 1. Introduction; 1.1 Thousand-core On-chip; 1.2 State-of-the-Art Many-core Microprocessors; 1.3 Memory-logic Integration; 1.3.1 2D Integration Challenges; 1.3.1.1 Scalability; 1.3.1.2 Channel Loss; 1.3.1.3 I/O Circuit Design; 1.3.1.4 Testing; 1.3.1.5 Thermal Management; 1.3.1.6 Power Management; 1.3.1.7 I/OManagement; 1.3.2 3D Integration; 1.3.3 2.5D Integration; 1.4 Organization of the Book; Part 1. Device Modeling; 2. Fabrication; 2.1 Introduction; 2.2 TSV Structure and Fabrication; 2.2.1 Structure Design; 2.2.1.1 Wafer Layout and Mask Design. 2.2.1.2 Electrical Structure Design2.2.1.3 Thermal Structure Design; 2.2.1.4 Dummy TSV Blocks; 2.2.2 Fabrication Process; 2.2.2.1 Electrical Structure Fabrication Process; 2.2.2.2 Thermal Structure Fabrication Process; 2.2.3 Process Control and Optimization; 2.2.3.1 DRIE Si Etch; 2.2.3.2 Dielectric Liner Deposition; 2.2.3.3 Ta Barrier/Cu Seed Layer Deposition and Cu ECP; 2.2.3.4 Cu CMP; 2.3 TSV Electrical Characterization; 2.3.1 Measurement Setup; 2.3.2 Conventional PETEOS Oxide Liner; 2.3.2.1 Electrical CV Measurement; 2.3.2.2 Electrical IV Measurement; 2.3.3 Black Diamond Low-k Liner. 2.3.3.1 Electrical CV Measurement2.3.3.2 Electrical IV Measurement; 2.3.4 Al2O3/Oxide Bi-layer Liner; 2.3.4.1 Electrical CV Measurement; 2.3.4.2 Electrical IV Measurement; 2.4 TSV Thermal Characterization Results; 2.4.1 Measurement Setup; 2.4.2 Cu-TSV Thermal Modeling; 2.4.3 Cu-TSV Induced Stress Modeling; 2.4.4 Cu-TSV Induced Stress Measurement by Micro-Raman Analysis; 2.5 TSI Structure and Fabrication; 2.5.1 Structure Design; 2.5.2 Fabrication Process; 2.6 Summary; 3. Device Model; 3.1 Introduction; 3.2 Nonlinear MOSCAP Model; 3.3 TSV Device Model; 3.3.1 Electrical Model. 3.3.2 Thermal Model3.3.3 Mechanical Model; 3.3.4 Delay Model; 3.3.4.1 Electrical-Thermal Coupled Delay Model; 3.3.4.2 Electrical-Mechanical Coupled Delay Model ; 3.3.4.3 Electrical-Thermal-Mechanical Coupled Delay Model; 3.3.5 Power Model; 3.4 TSI Device Model; 3.4.1 Delay Model; 3.4.1.1 T-line Model; 3.4.1.2 Delay of T-line; 3.4.2 Power Model; 3.4.2.1 TSV and TSI Comparison; 3.4.2.2 Energy-efficiency Analysis; 3.5 Summary; Part 2. Physical Design; 4. Macromodel; 4.1 Introduction; 4.2 Power and Thermal Integrity; 4.3 Macromodeling; 4.3.1 Complexity Compression. 4.3.1.1 Complexity Compression of States4.3.1.2 Complexity Compression of I/Os; 4.3.2 Parameterization; 4.4 Summary; 5. TSV Allocation; 5.1 Introduction; 5.2 Power Ground Design; 5.2.1 Problem Formulation; 5.2.2 Sensitivity based TSV Allocation; 5.3 Clock-treeDesign; 5.3.1 ProblemFormulation; 5.3.2 Sensitivity based TSV Allocation; 5.3.2.1 Reduction of Thermal Gradient; 5.3.2.2 Reduction of Stress Gradient; 5.3.2.3 Clock-skew Reduction; 5.4 Summary; 6. Testing; 6.1 Introduction; 6.2 3D IC Test; 6.2.1 System Architecture; 6.2.2 Problem Formulation. Three-dimensional integrated circuits. http://id.loc.gov/authorities/subjects/sh2011002115 Circuits intégrés tridimensionnels. TECHNOLOGY & ENGINEERING Mechanical. bisacsh Three-dimensional integrated circuits fast Tan, Chuan Seng. has work: Advances in 3D integrated circuits and systems (Text) https://id.oclc.org/worldcat/entity/E39PCGcgr7PtyKKHVGwccGT9rC https://id.oclc.org/worldcat/ontology/hasWork Print version: 9789814699006 9814699004 (DLC) 2015020144 (OCoLC)910475568 Series on emerging technologies in circuits and systems ; vol. 1. http://id.loc.gov/authorities/names/no2017022094 |
| spellingShingle | Yu, Hao (Electrical engineer) Advances in 3D integrated circuits and systems / Series on emerging technologies in circuits and systems ; Preface; 1. Introduction; 1.1 Thousand-core On-chip; 1.2 State-of-the-Art Many-core Microprocessors; 1.3 Memory-logic Integration; 1.3.1 2D Integration Challenges; 1.3.1.1 Scalability; 1.3.1.2 Channel Loss; 1.3.1.3 I/O Circuit Design; 1.3.1.4 Testing; 1.3.1.5 Thermal Management; 1.3.1.6 Power Management; 1.3.1.7 I/OManagement; 1.3.2 3D Integration; 1.3.3 2.5D Integration; 1.4 Organization of the Book; Part 1. Device Modeling; 2. Fabrication; 2.1 Introduction; 2.2 TSV Structure and Fabrication; 2.2.1 Structure Design; 2.2.1.1 Wafer Layout and Mask Design. 2.2.1.2 Electrical Structure Design2.2.1.3 Thermal Structure Design; 2.2.1.4 Dummy TSV Blocks; 2.2.2 Fabrication Process; 2.2.2.1 Electrical Structure Fabrication Process; 2.2.2.2 Thermal Structure Fabrication Process; 2.2.3 Process Control and Optimization; 2.2.3.1 DRIE Si Etch; 2.2.3.2 Dielectric Liner Deposition; 2.2.3.3 Ta Barrier/Cu Seed Layer Deposition and Cu ECP; 2.2.3.4 Cu CMP; 2.3 TSV Electrical Characterization; 2.3.1 Measurement Setup; 2.3.2 Conventional PETEOS Oxide Liner; 2.3.2.1 Electrical CV Measurement; 2.3.2.2 Electrical IV Measurement; 2.3.3 Black Diamond Low-k Liner. 2.3.3.1 Electrical CV Measurement2.3.3.2 Electrical IV Measurement; 2.3.4 Al2O3/Oxide Bi-layer Liner; 2.3.4.1 Electrical CV Measurement; 2.3.4.2 Electrical IV Measurement; 2.4 TSV Thermal Characterization Results; 2.4.1 Measurement Setup; 2.4.2 Cu-TSV Thermal Modeling; 2.4.3 Cu-TSV Induced Stress Modeling; 2.4.4 Cu-TSV Induced Stress Measurement by Micro-Raman Analysis; 2.5 TSI Structure and Fabrication; 2.5.1 Structure Design; 2.5.2 Fabrication Process; 2.6 Summary; 3. Device Model; 3.1 Introduction; 3.2 Nonlinear MOSCAP Model; 3.3 TSV Device Model; 3.3.1 Electrical Model. 3.3.2 Thermal Model3.3.3 Mechanical Model; 3.3.4 Delay Model; 3.3.4.1 Electrical-Thermal Coupled Delay Model; 3.3.4.2 Electrical-Mechanical Coupled Delay Model ; 3.3.4.3 Electrical-Thermal-Mechanical Coupled Delay Model; 3.3.5 Power Model; 3.4 TSI Device Model; 3.4.1 Delay Model; 3.4.1.1 T-line Model; 3.4.1.2 Delay of T-line; 3.4.2 Power Model; 3.4.2.1 TSV and TSI Comparison; 3.4.2.2 Energy-efficiency Analysis; 3.5 Summary; Part 2. Physical Design; 4. Macromodel; 4.1 Introduction; 4.2 Power and Thermal Integrity; 4.3 Macromodeling; 4.3.1 Complexity Compression. 4.3.1.1 Complexity Compression of States4.3.1.2 Complexity Compression of I/Os; 4.3.2 Parameterization; 4.4 Summary; 5. TSV Allocation; 5.1 Introduction; 5.2 Power Ground Design; 5.2.1 Problem Formulation; 5.2.2 Sensitivity based TSV Allocation; 5.3 Clock-treeDesign; 5.3.1 ProblemFormulation; 5.3.2 Sensitivity based TSV Allocation; 5.3.2.1 Reduction of Thermal Gradient; 5.3.2.2 Reduction of Stress Gradient; 5.3.2.3 Clock-skew Reduction; 5.4 Summary; 6. Testing; 6.1 Introduction; 6.2 3D IC Test; 6.2.1 System Architecture; 6.2.2 Problem Formulation. Three-dimensional integrated circuits. http://id.loc.gov/authorities/subjects/sh2011002115 Circuits intégrés tridimensionnels. TECHNOLOGY & ENGINEERING Mechanical. bisacsh Three-dimensional integrated circuits fast |
| subject_GND | http://id.loc.gov/authorities/subjects/sh2011002115 |
| title | Advances in 3D integrated circuits and systems / |
| title_auth | Advances in 3D integrated circuits and systems / |
| title_exact_search | Advances in 3D integrated circuits and systems / |
| title_full | Advances in 3D integrated circuits and systems / by Hao Yu (NTU, Singapore), Chuan-Seng Tan (NTU, Singapore). |
| title_fullStr | Advances in 3D integrated circuits and systems / by Hao Yu (NTU, Singapore), Chuan-Seng Tan (NTU, Singapore). |
| title_full_unstemmed | Advances in 3D integrated circuits and systems / by Hao Yu (NTU, Singapore), Chuan-Seng Tan (NTU, Singapore). |
| title_short | Advances in 3D integrated circuits and systems / |
| title_sort | advances in 3d integrated circuits and systems |
| topic | Three-dimensional integrated circuits. http://id.loc.gov/authorities/subjects/sh2011002115 Circuits intégrés tridimensionnels. TECHNOLOGY & ENGINEERING Mechanical. bisacsh Three-dimensional integrated circuits fast |
| topic_facet | Three-dimensional integrated circuits. Circuits intégrés tridimensionnels. TECHNOLOGY & ENGINEERING Mechanical. Three-dimensional integrated circuits |
| work_keys_str_mv | AT yuhao advancesin3dintegratedcircuitsandsystems AT tanchuanseng advancesin3dintegratedcircuitsandsystems |