The definitive guide to ARM Cortex-M3 and Cortex-M4 processors /:
This book presents the background of the ARM architecture and outlines the features of the processors such as the instruction set, interrupt-handling and also demonstrates how to program and utilize the advanced features available such as the Memory Protection Unit (MPU). Chapters on getting started...
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| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam :
Newnes,
2013.
|
| Ausgabe: | Third edition. |
| Schlagworte: | |
| Online-Zugang: | Volltext Volltext |
| Zusammenfassung: | This book presents the background of the ARM architecture and outlines the features of the processors such as the instruction set, interrupt-handling and also demonstrates how to program and utilize the advanced features available such as the Memory Protection Unit (MPU). Chapters on getting started with IAR, Keil, gcc and CooCox CoIDE tools help beginners develop program codes. Coverage also includes the important areas of software development such as using the low power features, handling information input/output, mixed language projects with assembly and C, and other advanced topics. Two new chapters on DSP features and CMSIS-DSP software libraries, covering DSP fundamentals and how to write DSP software for the Cortex-M4 processor, including examples of using the CMSIS-DSP library, as well as useful information about the DSP capability of the Cortex-M4 processorA new chapter on the Cortex-M4 floating point unit and how to use itA new chapter on using embedded OS (based on CMSIS-RTOS), as well as details of processor features to support OS operationsTopics on software porting from other architecturesA full range of easy-to-understand examples, diagrams and quick reference appendices. |
| Beschreibung: | Previous edition: 2010. |
| Beschreibung: | 1 online resource |
| Bibliographie: | Includes bibliographical references and index. |
| ISBN: | 9780124079182 0124079180 |
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| 100 | 1 | |a Yiu, Joseph, |e author. |1 https://id.oclc.org/worldcat/entity/E39PCjqVXfxfPWVDJtPvp7fpKb |0 http://id.loc.gov/authorities/names/nb2007027022 | |
| 245 | 1 | 4 | |a The definitive guide to ARM Cortex-M3 and Cortex-M4 processors / |c Joseph Yiu. |
| 250 | |a Third edition. | ||
| 264 | 1 | |a Amsterdam : |b Newnes, |c 2013. | |
| 300 | |a 1 online resource | ||
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| 500 | |a Previous edition: 2010. | ||
| 588 | 0 | |a Print version record. | |
| 520 | |a This book presents the background of the ARM architecture and outlines the features of the processors such as the instruction set, interrupt-handling and also demonstrates how to program and utilize the advanced features available such as the Memory Protection Unit (MPU). Chapters on getting started with IAR, Keil, gcc and CooCox CoIDE tools help beginners develop program codes. Coverage also includes the important areas of software development such as using the low power features, handling information input/output, mixed language projects with assembly and C, and other advanced topics. Two new chapters on DSP features and CMSIS-DSP software libraries, covering DSP fundamentals and how to write DSP software for the Cortex-M4 processor, including examples of using the CMSIS-DSP library, as well as useful information about the DSP capability of the Cortex-M4 processorA new chapter on the Cortex-M4 floating point unit and how to use itA new chapter on using embedded OS (based on CMSIS-RTOS), as well as details of processor features to support OS operationsTopics on software porting from other architecturesA full range of easy-to-understand examples, diagrams and quick reference appendices. | ||
| 505 | 0 | |a Machine generated contents note: ch. 1 Introduction to ARM® Cortex®-M Processors -- 1.1. What are the ARM® Cortex®-M processors? -- 1.1.1. The Cortex®-M3 and Cortex-M4 processors -- 1.1.2. The Cortex®-M processor family -- 1.1.3. Differences between a processor and a microcontroller -- 1.1.4. ARM® and the microcontroller vendors -- 1.1.5. Selecting Cortex®-M3 and Cortex-M4 microcontrollers -- 1.2. Advantages of the Cortex®-M processors -- 1.2.1. Low power -- 1.2.2. Performance -- 1.2.3. Energy efficiency -- 1.2.4. Code density -- 1.2.5. Interrupts -- 1.2.6. Ease of use, C friendly -- 1.2.7. Scalability -- 1.2.8. Debug features -- 1.2.9. OS support -- 1.2.10. Versatile system features -- 1.2.11. Software portability and reusability -- 1.2.12. Choices (devices, tools, OS, etc.) -- 1.3. Applications of the ARM® Cortex®-M processors -- 1.4. Resources for using ARM® processors and ARM microcontrollers -- 1.4.1. What can you find on the ARM® website -- 1.4.2. Documentation from the microcontroller vendors -- 1.4.3. Documentation from tools vendors -- 1.4.4. Other resources -- 1.5. Background and history -- 1.5.1.A brief history of ARM® -- 1.5.2. ARM® processor evolution -- 1.5.3. Architecture versions and Thumb® ISA -- 1.5.4. Processor naming -- 1.5.5. About the ARM® ecosystem -- ch. 2 Introduction to Embedded Software Development -- 2.1. What are inside typical ARM® microcontrollers? -- 2.2. What you need to start -- 2.2.1. Development suites -- 2.2.2. Development boards -- 2.2.3. Debug adaptor -- 2.2.4. Software device driver -- 2.2.5. Examples -- 2.2.6. Documentation and other resources -- 2.2.7. Other equipment -- 2.3. Software development flow -- 2.4.Compiling your applications -- 2.5. Software flow -- 2.5.1. Polling -- 2.5.2. Interrupt driven -- 2.5.3. Multi-tasking systems -- 2.6. Data types in C programming -- 2.7. Inputs, outputs, and peripherals accesses -- 2.8. Microcontroller interfaces -- 2.9. The Cortex® microcontroller software interface standard (CMSIS) -- 2.9.1. Introduction of CMSIS -- 2.9.2. Areas of standardization in CMSIS-Core -- 2.9.3.Organization of CMSIS-Core -- 2.9.4. How do I use CMSIS-Core? -- 2.9.5. Benefits of CMSIS-Core -- 2.9.6. Various versions of CMSIS -- ch. 3 Technical Overview -- 3.1. General information about the Cortex®-M3 and Cortex-M4 processors -- 3.1.1. Processor type -- 3.1.2. Processor architecture -- 3.1.3. Instruction set -- 3.1.4. Block diagram -- 3.1.5. Memory system -- 3.1.6. Interrupt and exception support -- 3.2. Features of the Cortex®-M3 and Cortex-M4 processors -- 3.2.1. Performance -- 3.2.2. Code density -- 3.2.3. Low power -- 3.2.4. Memory system -- 3.2.5. Memory protection unit -- 3.2.6. Interrupt handling -- 3.2.7. OS support and system level features -- 3.2.8. Cortex®-M4 specific features -- 3.2.9. Ease of use -- 3.2.10. Debug support -- 3.2.11. Scalability -- 3.2.12.Compatibility -- ch. 4 Architecture -- 4.1. Introduction to the architecture -- 4.2. Programmer's model -- 4.2.1. Operation modes and states -- 4.2.2. Registers -- 4.2.3. Special registers -- 4.2.4. Floating point registers -- 4.3. Behavior of the application program status register (APSR) -- 4.3.1. Integer status flags -- 4.3.2.Q status flag -- 4.3.3. GE bits -- 4.4. Memory system -- 4.4.1. Memory system features -- 4.4.2. Memory map -- 4.4.3. Stack memory -- 4.4.4. Memory protection unit (MPU) -- 4.5. Exceptions and interrupts -- 4.5.1. What are exceptions? -- 4.5.2. Nested vectored interrupt controller (NVIC) -- 4.5.3. Vector table -- 4.5.4. Fault handling -- 4.6. System control block (SCB) -- 4.7. Debug -- 4.8. Reset and reset sequence -- | |
| 505 | 0 | |a Note continued: ch. 5 Instruction Set -- 5.1. Background to the instruction set in ARM® Cortex®-M processors -- 5.2.Comparison of the instruction set in ARM® Cortex®-M processors -- 5.3. Understanding the assembly language syntax -- 5.4. Use of a suffix in instructions -- 5.5. Unified assembly language (UAL) -- 5.6. Instruction set -- 5.6.1. Moving data within the processor -- 5.6.2. Memory access instructions -- 5.6.3. Arithmetic operations -- 5.6.4. Logic operations -- 5.6.5. Shift and rotate instructions -- 5.6.6. Data conversion operations (extend and reverse ordering) -- 5.6.7. Bit-field processing instructions -- 5.6.8.Compare and test -- 5.6.9. Program flow control -- 5.6.10. Saturation operations -- 5.6.11. Exception-related instructions -- 5.6.12. Sleep mode-related instructions -- 5.6.13. Memory barrier instructions -- 5.6.14. Other instructions -- 5.6.15. Unsupported instructions -- 5.7. Cortex®-M4-specific instructions -- 5.7.1. Overview of enhanced DSP extension in Cortex-M4 -- 5.7.2. SIMD and saturating instructions -- 5.7.3. Multiply and MAC instructions -- 5.7.4. Packing and unpacking -- 5.7.5. Floating point instructions -- 5.8. Barrel shifter -- 5.9. Accessing special instructions and special registers in programming -- 5.9.1. Overview -- 5.9.2. Intrinsic functions -- 5.9.3. Inline assembler and embedded assembler -- 5.9.4. Using other compiler-specific features -- 5.9.5. Access of special registers -- ch. 6 Memory System -- 6.1. Overview of memory system features -- 6.2. Memory map -- 6.3. Connecting the processor to memory and peripherals -- 6.4. Memory requirements -- 6.5. Memory endianness -- 6.6. Data alignment and unaligned data access support -- 6.7. Bit-band operations -- 6.7.1. Overview -- 6.7.2. Advantages of bit-band operations -- 6.7.3. Bit-band operation of different data sizes -- 6.7.4. Bit-band operations in C programs -- 6.8. Default memory access permissions -- 6.9. Memory access attributes -- 6.10. Exclusive accesses -- 6.11. Memory barriers -- 6.12. Memory system in a microcontroller -- ch. 7 Exceptions and Interrupts -- 7.1. Overview of exceptions and interrupts -- 7.2. Exception types -- 7.3. Overview of interrupt management -- 7.4. Definitions of priority -- 7.5. Vector table and vector table relocation -- 7.6. Interrupt inputs and pending behaviors -- 7.7. Exception sequence overview -- 7.7.1. Acceptance of exception request -- 7.7.2. Exception entrance sequence -- 7.7.3. Exception handler execution -- 7.7.4. Exception return -- 7.8. Details of NVIC registers for interrupt control -- 7.8.1. Summary -- 7.8.2. Interrupt enable registers -- 7.8.3. Interrupt set pending and clear pending -- 7.8.4. Active status -- 7.8.5. Priority level -- 7.8.6. Software trigger interrupt register -- 7.8.7. Interrupt controller type register -- 7.9. Details of SCB registers for exception and interrupt control -- 7.9.1. Summary of the SCB registers -- 7.9.2. Interrupt control and state register (ICSR) -- 7.9.3. Vector table offset register (VTOR) -- 7.9.4. Application interrupt and reset control register (AIRCR) -- 7.9.5. System handler priority registers (SCB-> SHP[0 to 11]) -- 7.9.6. System handler control and state register (SCB-> SHCSR) -- 7.10. Details of special registers for exception or interrupt masking -- 7.10.1. PRIMASK -- 7.10.2. FAULTMASK -- 7.10.3. BASEPRI -- 7.11. Example procedures in setting up interrupts -- 7.11.1. Simple cases -- 7.11.2. With vector table relocation -- 7.12. Software interrupts -- 7.13. Tips and hints -- | |
| 505 | 0 | |a Note continued: ch. 8 Exception Handling in Detail -- 8.1. Introduction -- 8.1.1. About this chapter -- 8.1.2. Exception handler in C -- 8.1.3. Stack frames -- 8.1.4. EXC_RETURN -- 8.2. Exception sequences -- 8.2.1. Exception entrance and stacking -- 8.2.2. Exception return and unstacking -- 8.3. Interrupt latency and exception handling optimization -- 8.3.1. What is interrupt latency? -- 8.3.2. Interrupts at multiple-cycle instructions -- 8.3.3. Tail chaining -- 8.3.4. Late arrival -- 8.3.5. Pop preemption -- 8.3.6. Lazy stacking -- ch. 9 Low Power and System Control Features -- 9.1. Low power designs -- 9.1.1. What does low power mean in microcontrollers? -- 9.1.2. Low power system requirements -- 9.1.3. Low power characteristics of the Cortex®-M3 and Cortex-M4 processors -- 9.2. Low power features -- 9.2.1. Sleep modes -- 9.2.2. System control register (SCR) -- 9.2.3. Entering sleep modes -- 9.2.4. Wake-up conditions -- 9.2.5. Sleep-on-Exit feature -- 9.2.6. Send event on pend (SEVONPEND) -- 9.2.7. Sleep extension/wake-up delay -- 9.2.8. Wake-up interrupt controller (WIC) -- 9.2.9. Event communication interface -- 9.3. Using WFT and WFE instructions in programming -- 9.3.1. When to use WFI -- 9.3.2. Using WFE -- 9.4. Developing low power applications -- 9.4.1. Reducing the active power -- 9.4.2. Reduction of active cycles -- 9.4.3. Sleep mode current reduction -- 9.5. The SysTick timer -- 9.5.1. Why have a SysTick timer -- 9.5.2. Operations of the SysTick timer -- 9.5.3. Using the SysTick timer -- 9.5.4. Other considerations -- 9.6. Self-reset -- 9.7. CPU ID base register -- 9.8. Configuration control register -- 9.8.1. Overview of CCR -- 9.8.2. Stkalign bit -- 9.8.3. Bfhfnmign bit -- 9.8.4. DIV_0_TRP bit -- 9.8.5. Unalign_Trp bit -- 9.8.6. Usersetmpend bit -- 9.8.7. Nonbasethrdena bit -- 9.9. Auxiliary control register -- 9.10. Co-processor access control register -- ch. 10 OS Support Features -- 10.1. Overview of OS support features -- 10.2. Shadowed stack pointer -- 10.3. SVC exception -- 10.4. PendSV exception -- 10.5. Context switching in action -- 10.6. Exclusive accesses and embedded OS -- ch. 11 Memory Protection Unit (MPU) -- 11.1. Overview of the MPU -- 11.1.1. About the MPU -- 11.1.2. Using the MPU -- 11.2. MPU registers -- 11.2.1. MPU type register -- 11.2.2. MPU control register -- 11.2.3. MPU region number register -- 11.2.4. MPU region base address register -- 11.2.5. MPU region base attribute and size register -- 11.2.6. MPU alias registers -- 11.3. Setting up the MPU -- 11.4. Memory barrier and MPU configuration -- 11.5. Using sub-region disable -- 11.5.1. Allow efficient memory separation -- 11.5.2. Reduce the total number of regions needed -- 11.6. Considerations when using MPU -- 11.6.1. Program code -- 11.6.2. Data memory -- 11.6.3. Peripherals -- 11.7. Other usages of the MPU -- 11.8.Comparing with the MPU in the Cortex®-M0+ processor -- ch. 12 Fault Exceptions and Fault Handling -- 12.1. Overview of fault exceptions -- 12.2. Causes of faults -- 12.2.1. Memory management (MemManage) faults -- 12.2.2. Bus faults -- 12.2.3. Usage | |
| 505 | 0 | |a Note continued: 24.3.4. Pre-compiled object files and libraries -- 24.3.5. Optimization -- 24.4. Porting software between different Cortex®-M processors -- 24.4.1. Differences between different Cortex®-M processors -- 24.4.2. Required software changes -- 24.4.3. Embedded OS -- 24.4.4. Creating portable program code for the Cortex®-M processors. | |
| 504 | |a Includes bibliographical references and index. | ||
| 650 | 0 | |a Embedded computer systems. |0 http://id.loc.gov/authorities/subjects/sh87006632 | |
| 650 | 0 | |a Microprocessors. |0 http://id.loc.gov/authorities/subjects/sh85084898 | |
| 650 | 6 | |a Systèmes enfouis (Informatique) | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Mechanical. |2 bisacsh | |
| 650 | 7 | |a Embedded computer systems |2 fast | |
| 650 | 7 | |a Microprocessors |2 fast | |
| 758 | |i has work: |a The definitive guide to ARM® Cortex®-M3 and Cortex-M4 processors (Text) |1 https://id.oclc.org/worldcat/entity/E39PCFQmcqrFkMpxFdbyYK4b7d |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
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| contents | Machine generated contents note: ch. 1 Introduction to ARM® Cortex®-M Processors -- 1.1. What are the ARM® Cortex®-M processors? -- 1.1.1. The Cortex®-M3 and Cortex-M4 processors -- 1.1.2. The Cortex®-M processor family -- 1.1.3. Differences between a processor and a microcontroller -- 1.1.4. ARM® and the microcontroller vendors -- 1.1.5. Selecting Cortex®-M3 and Cortex-M4 microcontrollers -- 1.2. Advantages of the Cortex®-M processors -- 1.2.1. Low power -- 1.2.2. Performance -- 1.2.3. Energy efficiency -- 1.2.4. Code density -- 1.2.5. Interrupts -- 1.2.6. Ease of use, C friendly -- 1.2.7. Scalability -- 1.2.8. Debug features -- 1.2.9. OS support -- 1.2.10. Versatile system features -- 1.2.11. Software portability and reusability -- 1.2.12. Choices (devices, tools, OS, etc.) -- 1.3. Applications of the ARM® Cortex®-M processors -- 1.4. Resources for using ARM® processors and ARM microcontrollers -- 1.4.1. What can you find on the ARM® website -- 1.4.2. Documentation from the microcontroller vendors -- 1.4.3. Documentation from tools vendors -- 1.4.4. Other resources -- 1.5. Background and history -- 1.5.1.A brief history of ARM® -- 1.5.2. ARM® processor evolution -- 1.5.3. Architecture versions and Thumb® ISA -- 1.5.4. Processor naming -- 1.5.5. About the ARM® ecosystem -- ch. 2 Introduction to Embedded Software Development -- 2.1. What are inside typical ARM® microcontrollers? -- 2.2. What you need to start -- 2.2.1. Development suites -- 2.2.2. Development boards -- 2.2.3. Debug adaptor -- 2.2.4. Software device driver -- 2.2.5. Examples -- 2.2.6. Documentation and other resources -- 2.2.7. Other equipment -- 2.3. Software development flow -- 2.4.Compiling your applications -- 2.5. Software flow -- 2.5.1. Polling -- 2.5.2. Interrupt driven -- 2.5.3. Multi-tasking systems -- 2.6. Data types in C programming -- 2.7. Inputs, outputs, and peripherals accesses -- 2.8. Microcontroller interfaces -- 2.9. The Cortex® microcontroller software interface standard (CMSIS) -- 2.9.1. Introduction of CMSIS -- 2.9.2. Areas of standardization in CMSIS-Core -- 2.9.3.Organization of CMSIS-Core -- 2.9.4. How do I use CMSIS-Core? -- 2.9.5. Benefits of CMSIS-Core -- 2.9.6. Various versions of CMSIS -- ch. 3 Technical Overview -- 3.1. General information about the Cortex®-M3 and Cortex-M4 processors -- 3.1.1. Processor type -- 3.1.2. Processor architecture -- 3.1.3. Instruction set -- 3.1.4. Block diagram -- 3.1.5. Memory system -- 3.1.6. Interrupt and exception support -- 3.2. Features of the Cortex®-M3 and Cortex-M4 processors -- 3.2.1. Performance -- 3.2.2. Code density -- 3.2.3. Low power -- 3.2.4. Memory system -- 3.2.5. Memory protection unit -- 3.2.6. Interrupt handling -- 3.2.7. OS support and system level features -- 3.2.8. Cortex®-M4 specific features -- 3.2.9. Ease of use -- 3.2.10. Debug support -- 3.2.11. Scalability -- 3.2.12.Compatibility -- ch. 4 Architecture -- 4.1. Introduction to the architecture -- 4.2. Programmer's model -- 4.2.1. Operation modes and states -- 4.2.2. Registers -- 4.2.3. Special registers -- 4.2.4. Floating point registers -- 4.3. Behavior of the application program status register (APSR) -- 4.3.1. Integer status flags -- 4.3.2.Q status flag -- 4.3.3. GE bits -- 4.4. Memory system -- 4.4.1. Memory system features -- 4.4.2. Memory map -- 4.4.3. Stack memory -- 4.4.4. Memory protection unit (MPU) -- 4.5. Exceptions and interrupts -- 4.5.1. What are exceptions? -- 4.5.2. Nested vectored interrupt controller (NVIC) -- 4.5.3. Vector table -- 4.5.4. Fault handling -- 4.6. System control block (SCB) -- 4.7. Debug -- 4.8. Reset and reset sequence -- Note continued: ch. 5 Instruction Set -- 5.1. Background to the instruction set in ARM® Cortex®-M processors -- 5.2.Comparison of the instruction set in ARM® Cortex®-M processors -- 5.3. Understanding the assembly language syntax -- 5.4. Use of a suffix in instructions -- 5.5. Unified assembly language (UAL) -- 5.6. Instruction set -- 5.6.1. Moving data within the processor -- 5.6.2. Memory access instructions -- 5.6.3. Arithmetic operations -- 5.6.4. Logic operations -- 5.6.5. Shift and rotate instructions -- 5.6.6. Data conversion operations (extend and reverse ordering) -- 5.6.7. Bit-field processing instructions -- 5.6.8.Compare and test -- 5.6.9. Program flow control -- 5.6.10. Saturation operations -- 5.6.11. Exception-related instructions -- 5.6.12. Sleep mode-related instructions -- 5.6.13. Memory barrier instructions -- 5.6.14. Other instructions -- 5.6.15. Unsupported instructions -- 5.7. Cortex®-M4-specific instructions -- 5.7.1. Overview of enhanced DSP extension in Cortex-M4 -- 5.7.2. SIMD and saturating instructions -- 5.7.3. Multiply and MAC instructions -- 5.7.4. Packing and unpacking -- 5.7.5. Floating point instructions -- 5.8. Barrel shifter -- 5.9. Accessing special instructions and special registers in programming -- 5.9.1. Overview -- 5.9.2. Intrinsic functions -- 5.9.3. Inline assembler and embedded assembler -- 5.9.4. Using other compiler-specific features -- 5.9.5. Access of special registers -- ch. 6 Memory System -- 6.1. Overview of memory system features -- 6.2. Memory map -- 6.3. Connecting the processor to memory and peripherals -- 6.4. Memory requirements -- 6.5. Memory endianness -- 6.6. Data alignment and unaligned data access support -- 6.7. Bit-band operations -- 6.7.1. Overview -- 6.7.2. Advantages of bit-band operations -- 6.7.3. Bit-band operation of different data sizes -- 6.7.4. Bit-band operations in C programs -- 6.8. Default memory access permissions -- 6.9. Memory access attributes -- 6.10. Exclusive accesses -- 6.11. Memory barriers -- 6.12. Memory system in a microcontroller -- ch. 7 Exceptions and Interrupts -- 7.1. Overview of exceptions and interrupts -- 7.2. Exception types -- 7.3. Overview of interrupt management -- 7.4. Definitions of priority -- 7.5. Vector table and vector table relocation -- 7.6. Interrupt inputs and pending behaviors -- 7.7. Exception sequence overview -- 7.7.1. Acceptance of exception request -- 7.7.2. Exception entrance sequence -- 7.7.3. Exception handler execution -- 7.7.4. Exception return -- 7.8. Details of NVIC registers for interrupt control -- 7.8.1. Summary -- 7.8.2. Interrupt enable registers -- 7.8.3. Interrupt set pending and clear pending -- 7.8.4. Active status -- 7.8.5. Priority level -- 7.8.6. Software trigger interrupt register -- 7.8.7. Interrupt controller type register -- 7.9. Details of SCB registers for exception and interrupt control -- 7.9.1. Summary of the SCB registers -- 7.9.2. Interrupt control and state register (ICSR) -- 7.9.3. Vector table offset register (VTOR) -- 7.9.4. Application interrupt and reset control register (AIRCR) -- 7.9.5. System handler priority registers (SCB-> SHP[0 to 11]) -- 7.9.6. System handler control and state register (SCB-> SHCSR) -- 7.10. Details of special registers for exception or interrupt masking -- 7.10.1. PRIMASK -- 7.10.2. FAULTMASK -- 7.10.3. BASEPRI -- 7.11. Example procedures in setting up interrupts -- 7.11.1. Simple cases -- 7.11.2. With vector table relocation -- 7.12. Software interrupts -- 7.13. Tips and hints -- Note continued: ch. 8 Exception Handling in Detail -- 8.1. Introduction -- 8.1.1. About this chapter -- 8.1.2. Exception handler in C -- 8.1.3. Stack frames -- 8.1.4. EXC_RETURN -- 8.2. Exception sequences -- 8.2.1. Exception entrance and stacking -- 8.2.2. Exception return and unstacking -- 8.3. Interrupt latency and exception handling optimization -- 8.3.1. What is interrupt latency? -- 8.3.2. Interrupts at multiple-cycle instructions -- 8.3.3. Tail chaining -- 8.3.4. Late arrival -- 8.3.5. Pop preemption -- 8.3.6. Lazy stacking -- ch. 9 Low Power and System Control Features -- 9.1. Low power designs -- 9.1.1. What does low power mean in microcontrollers? -- 9.1.2. Low power system requirements -- 9.1.3. Low power characteristics of the Cortex®-M3 and Cortex-M4 processors -- 9.2. Low power features -- 9.2.1. Sleep modes -- 9.2.2. System control register (SCR) -- 9.2.3. Entering sleep modes -- 9.2.4. Wake-up conditions -- 9.2.5. Sleep-on-Exit feature -- 9.2.6. Send event on pend (SEVONPEND) -- 9.2.7. Sleep extension/wake-up delay -- 9.2.8. Wake-up interrupt controller (WIC) -- 9.2.9. Event communication interface -- 9.3. Using WFT and WFE instructions in programming -- 9.3.1. When to use WFI -- 9.3.2. Using WFE -- 9.4. Developing low power applications -- 9.4.1. Reducing the active power -- 9.4.2. Reduction of active cycles -- 9.4.3. Sleep mode current reduction -- 9.5. The SysTick timer -- 9.5.1. Why have a SysTick timer -- 9.5.2. Operations of the SysTick timer -- 9.5.3. Using the SysTick timer -- 9.5.4. Other considerations -- 9.6. Self-reset -- 9.7. CPU ID base register -- 9.8. Configuration control register -- 9.8.1. Overview of CCR -- 9.8.2. Stkalign bit -- 9.8.3. Bfhfnmign bit -- 9.8.4. DIV_0_TRP bit -- 9.8.5. Unalign_Trp bit -- 9.8.6. Usersetmpend bit -- 9.8.7. Nonbasethrdena bit -- 9.9. Auxiliary control register -- 9.10. Co-processor access control register -- ch. 10 OS Support Features -- 10.1. Overview of OS support features -- 10.2. Shadowed stack pointer -- 10.3. SVC exception -- 10.4. PendSV exception -- 10.5. Context switching in action -- 10.6. Exclusive accesses and embedded OS -- ch. 11 Memory Protection Unit (MPU) -- 11.1. Overview of the MPU -- 11.1.1. About the MPU -- 11.1.2. Using the MPU -- 11.2. MPU registers -- 11.2.1. MPU type register -- 11.2.2. MPU control register -- 11.2.3. MPU region number register -- 11.2.4. MPU region base address register -- 11.2.5. MPU region base attribute and size register -- 11.2.6. MPU alias registers -- 11.3. Setting up the MPU -- 11.4. Memory barrier and MPU configuration -- 11.5. Using sub-region disable -- 11.5.1. Allow efficient memory separation -- 11.5.2. Reduce the total number of regions needed -- 11.6. Considerations when using MPU -- 11.6.1. Program code -- 11.6.2. Data memory -- 11.6.3. Peripherals -- 11.7. Other usages of the MPU -- 11.8.Comparing with the MPU in the Cortex®-M0+ processor -- ch. 12 Fault Exceptions and Fault Handling -- 12.1. Overview of fault exceptions -- 12.2. Causes of faults -- 12.2.1. Memory management (MemManage) faults -- 12.2.2. Bus faults -- 12.2.3. Usage Note continued: 24.3.4. Pre-compiled object files and libraries -- 24.3.5. Optimization -- 24.4. Porting software between different Cortex®-M processors -- 24.4.1. Differences between different Cortex®-M processors -- 24.4.2. Required software changes -- 24.4.3. Embedded OS -- 24.4.4. Creating portable program code for the Cortex®-M processors. |
| ctrlnum | (OCoLC)860906302 |
| dewey-full | 621.3916 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3916 |
| dewey-search | 621.3916 |
| dewey-sort | 3621.3916 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | Third edition. |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>14740cam a2200637 i 4500</leader><controlfield tag="001">ZDB-4-EBA-ocn860906302</controlfield><controlfield tag="003">OCoLC</controlfield><controlfield tag="005">20240705115654.0</controlfield><controlfield tag="006">m o d </controlfield><controlfield tag="007">cr cnu---unuuu</controlfield><controlfield tag="008">131017s2013 ne a ob 001 0 eng d</controlfield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">N$T</subfield><subfield code="b">eng</subfield><subfield code="e">rda</subfield><subfield code="e">pn</subfield><subfield code="c">N$T</subfield><subfield code="d">OPELS</subfield><subfield code="d">YDXCP</subfield><subfield code="d">CDX</subfield><subfield code="d">UPM</subfield><subfield code="d">OCLCF</subfield><subfield code="d">UIU</subfield><subfield code="d">TEFOD</subfield><subfield code="d">REB</subfield><subfield code="d">CNSPO</subfield><subfield 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code="a">(OCoLC)860906302</subfield><subfield code="z">(OCoLC)865330420</subfield><subfield code="z">(OCoLC)872699135</subfield><subfield code="z">(OCoLC)876280732</subfield></datafield><datafield tag="037" ind1=" " ind2=" "><subfield code="a">5689417B-3224-49B2-8048-11994617AC81</subfield><subfield code="b">OverDrive, Inc.</subfield><subfield code="n">http://www.overdrive.com</subfield></datafield><datafield tag="050" ind1=" " ind2="4"><subfield code="a">TK7895.E42</subfield></datafield><datafield tag="072" ind1=" " ind2="7"><subfield code="a">TEC</subfield><subfield code="x">009070</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="082" ind1="7" ind2=" "><subfield code="a">621.3916</subfield><subfield code="2">23</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">MAIN</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Yiu, Joseph,</subfield><subfield code="e">author.</subfield><subfield code="1">https://id.oclc.org/worldcat/entity/E39PCjqVXfxfPWVDJtPvp7fpKb</subfield><subfield code="0">http://id.loc.gov/authorities/names/nb2007027022</subfield></datafield><datafield tag="245" ind1="1" ind2="4"><subfield code="a">The definitive guide to ARM Cortex-M3 and Cortex-M4 processors /</subfield><subfield code="c">Joseph Yiu.</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">Third edition.</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Amsterdam :</subfield><subfield code="b">Newnes,</subfield><subfield code="c">2013.</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 online resource</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">computer</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">online resource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Previous edition: 2010.</subfield></datafield><datafield tag="588" ind1="0" ind2=" "><subfield code="a">Print version record.</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This book presents the background of the ARM architecture and outlines the features of the processors such as the instruction set, interrupt-handling and also demonstrates how to program and utilize the advanced features available such as the Memory Protection Unit (MPU). Chapters on getting started with IAR, Keil, gcc and CooCox CoIDE tools help beginners develop program codes. Coverage also includes the important areas of software development such as using the low power features, handling information input/output, mixed language projects with assembly and C, and other advanced topics. Two new chapters on DSP features and CMSIS-DSP software libraries, covering DSP fundamentals and how to write DSP software for the Cortex-M4 processor, including examples of using the CMSIS-DSP library, as well as useful information about the DSP capability of the Cortex-M4 processorA new chapter on the Cortex-M4 floating point unit and how to use itA new chapter on using embedded OS (based on CMSIS-RTOS), as well as details of processor features to support OS operationsTopics on software porting from other architecturesA full range of easy-to-understand examples, diagrams and quick reference appendices.</subfield></datafield><datafield tag="505" ind1="0" ind2=" "><subfield code="a">Machine generated contents note: ch. 1 Introduction to ARM® Cortex®-M Processors -- 1.1. What are the ARM® Cortex®-M processors? -- 1.1.1. The Cortex®-M3 and Cortex-M4 processors -- 1.1.2. The Cortex®-M processor family -- 1.1.3. Differences between a processor and a microcontroller -- 1.1.4. ARM® and the microcontroller vendors -- 1.1.5. Selecting Cortex®-M3 and Cortex-M4 microcontrollers -- 1.2. Advantages of the Cortex®-M processors -- 1.2.1. Low power -- 1.2.2. Performance -- 1.2.3. Energy efficiency -- 1.2.4. Code density -- 1.2.5. Interrupts -- 1.2.6. Ease of use, C friendly -- 1.2.7. Scalability -- 1.2.8. Debug features -- 1.2.9. OS support -- 1.2.10. Versatile system features -- 1.2.11. Software portability and reusability -- 1.2.12. Choices (devices, tools, OS, etc.) -- 1.3. Applications of the ARM® Cortex®-M processors -- 1.4. Resources for using ARM® processors and ARM microcontrollers -- 1.4.1. What can you find on the ARM® website -- 1.4.2. Documentation from the microcontroller vendors -- 1.4.3. Documentation from tools vendors -- 1.4.4. Other resources -- 1.5. Background and history -- 1.5.1.A brief history of ARM® -- 1.5.2. ARM® processor evolution -- 1.5.3. Architecture versions and Thumb® ISA -- 1.5.4. Processor naming -- 1.5.5. About the ARM® ecosystem -- ch. 2 Introduction to Embedded Software Development -- 2.1. What are inside typical ARM® microcontrollers? -- 2.2. What you need to start -- 2.2.1. Development suites -- 2.2.2. Development boards -- 2.2.3. Debug adaptor -- 2.2.4. Software device driver -- 2.2.5. Examples -- 2.2.6. Documentation and other resources -- 2.2.7. Other equipment -- 2.3. Software development flow -- 2.4.Compiling your applications -- 2.5. Software flow -- 2.5.1. Polling -- 2.5.2. Interrupt driven -- 2.5.3. Multi-tasking systems -- 2.6. Data types in C programming -- 2.7. Inputs, outputs, and peripherals accesses -- 2.8. Microcontroller interfaces -- 2.9. The Cortex® microcontroller software interface standard (CMSIS) -- 2.9.1. Introduction of CMSIS -- 2.9.2. Areas of standardization in CMSIS-Core -- 2.9.3.Organization of CMSIS-Core -- 2.9.4. How do I use CMSIS-Core? -- 2.9.5. Benefits of CMSIS-Core -- 2.9.6. Various versions of CMSIS -- ch. 3 Technical Overview -- 3.1. General information about the Cortex®-M3 and Cortex-M4 processors -- 3.1.1. Processor type -- 3.1.2. Processor architecture -- 3.1.3. Instruction set -- 3.1.4. Block diagram -- 3.1.5. Memory system -- 3.1.6. Interrupt and exception support -- 3.2. Features of the Cortex®-M3 and Cortex-M4 processors -- 3.2.1. Performance -- 3.2.2. Code density -- 3.2.3. Low power -- 3.2.4. Memory system -- 3.2.5. Memory protection unit -- 3.2.6. Interrupt handling -- 3.2.7. OS support and system level features -- 3.2.8. Cortex®-M4 specific features -- 3.2.9. Ease of use -- 3.2.10. Debug support -- 3.2.11. Scalability -- 3.2.12.Compatibility -- ch. 4 Architecture -- 4.1. Introduction to the architecture -- 4.2. Programmer's model -- 4.2.1. Operation modes and states -- 4.2.2. Registers -- 4.2.3. Special registers -- 4.2.4. Floating point registers -- 4.3. Behavior of the application program status register (APSR) -- 4.3.1. Integer status flags -- 4.3.2.Q status flag -- 4.3.3. GE bits -- 4.4. Memory system -- 4.4.1. Memory system features -- 4.4.2. Memory map -- 4.4.3. Stack memory -- 4.4.4. Memory protection unit (MPU) -- 4.5. Exceptions and interrupts -- 4.5.1. What are exceptions? -- 4.5.2. Nested vectored interrupt controller (NVIC) -- 4.5.3. Vector table -- 4.5.4. Fault handling -- 4.6. System control block (SCB) -- 4.7. Debug -- 4.8. Reset and reset sequence --</subfield></datafield><datafield tag="505" ind1="0" ind2=" "><subfield code="a">Note continued: ch. 5 Instruction Set -- 5.1. Background to the instruction set in ARM® Cortex®-M processors -- 5.2.Comparison of the instruction set in ARM® Cortex®-M processors -- 5.3. Understanding the assembly language syntax -- 5.4. Use of a suffix in instructions -- 5.5. Unified assembly language (UAL) -- 5.6. Instruction set -- 5.6.1. Moving data within the processor -- 5.6.2. Memory access instructions -- 5.6.3. Arithmetic operations -- 5.6.4. Logic operations -- 5.6.5. Shift and rotate instructions -- 5.6.6. Data conversion operations (extend and reverse ordering) -- 5.6.7. Bit-field processing instructions -- 5.6.8.Compare and test -- 5.6.9. Program flow control -- 5.6.10. Saturation operations -- 5.6.11. Exception-related instructions -- 5.6.12. Sleep mode-related instructions -- 5.6.13. Memory barrier instructions -- 5.6.14. Other instructions -- 5.6.15. Unsupported instructions -- 5.7. Cortex®-M4-specific instructions -- 5.7.1. Overview of enhanced DSP extension in Cortex-M4 -- 5.7.2. SIMD and saturating instructions -- 5.7.3. Multiply and MAC instructions -- 5.7.4. Packing and unpacking -- 5.7.5. Floating point instructions -- 5.8. Barrel shifter -- 5.9. Accessing special instructions and special registers in programming -- 5.9.1. Overview -- 5.9.2. Intrinsic functions -- 5.9.3. Inline assembler and embedded assembler -- 5.9.4. Using other compiler-specific features -- 5.9.5. Access of special registers -- ch. 6 Memory System -- 6.1. Overview of memory system features -- 6.2. Memory map -- 6.3. Connecting the processor to memory and peripherals -- 6.4. Memory requirements -- 6.5. Memory endianness -- 6.6. Data alignment and unaligned data access support -- 6.7. Bit-band operations -- 6.7.1. Overview -- 6.7.2. Advantages of bit-band operations -- 6.7.3. Bit-band operation of different data sizes -- 6.7.4. Bit-band operations in C programs -- 6.8. Default memory access permissions -- 6.9. Memory access attributes -- 6.10. Exclusive accesses -- 6.11. Memory barriers -- 6.12. Memory system in a microcontroller -- ch. 7 Exceptions and Interrupts -- 7.1. Overview of exceptions and interrupts -- 7.2. Exception types -- 7.3. Overview of interrupt management -- 7.4. Definitions of priority -- 7.5. Vector table and vector table relocation -- 7.6. Interrupt inputs and pending behaviors -- 7.7. Exception sequence overview -- 7.7.1. Acceptance of exception request -- 7.7.2. Exception entrance sequence -- 7.7.3. Exception handler execution -- 7.7.4. Exception return -- 7.8. Details of NVIC registers for interrupt control -- 7.8.1. Summary -- 7.8.2. Interrupt enable registers -- 7.8.3. Interrupt set pending and clear pending -- 7.8.4. Active status -- 7.8.5. Priority level -- 7.8.6. Software trigger interrupt register -- 7.8.7. Interrupt controller type register -- 7.9. Details of SCB registers for exception and interrupt control -- 7.9.1. Summary of the SCB registers -- 7.9.2. Interrupt control and state register (ICSR) -- 7.9.3. Vector table offset register (VTOR) -- 7.9.4. Application interrupt and reset control register (AIRCR) -- 7.9.5. System handler priority registers (SCB-> SHP[0 to 11]) -- 7.9.6. System handler control and state register (SCB-> SHCSR) -- 7.10. Details of special registers for exception or interrupt masking -- 7.10.1. PRIMASK -- 7.10.2. FAULTMASK -- 7.10.3. BASEPRI -- 7.11. Example procedures in setting up interrupts -- 7.11.1. Simple cases -- 7.11.2. With vector table relocation -- 7.12. Software interrupts -- 7.13. Tips and hints --</subfield></datafield><datafield tag="505" ind1="0" ind2=" "><subfield code="a">Note continued: ch. 8 Exception Handling in Detail -- 8.1. Introduction -- 8.1.1. About this chapter -- 8.1.2. Exception handler in C -- 8.1.3. Stack frames -- 8.1.4. EXC_RETURN -- 8.2. Exception sequences -- 8.2.1. Exception entrance and stacking -- 8.2.2. Exception return and unstacking -- 8.3. Interrupt latency and exception handling optimization -- 8.3.1. What is interrupt latency? -- 8.3.2. Interrupts at multiple-cycle instructions -- 8.3.3. Tail chaining -- 8.3.4. Late arrival -- 8.3.5. Pop preemption -- 8.3.6. Lazy stacking -- ch. 9 Low Power and System Control Features -- 9.1. Low power designs -- 9.1.1. What does low power mean in microcontrollers? -- 9.1.2. Low power system requirements -- 9.1.3. Low power characteristics of the Cortex®-M3 and Cortex-M4 processors -- 9.2. Low power features -- 9.2.1. Sleep modes -- 9.2.2. System control register (SCR) -- 9.2.3. Entering sleep modes -- 9.2.4. Wake-up conditions -- 9.2.5. Sleep-on-Exit feature -- 9.2.6. Send event on pend (SEVONPEND) -- 9.2.7. Sleep extension/wake-up delay -- 9.2.8. Wake-up interrupt controller (WIC) -- 9.2.9. Event communication interface -- 9.3. Using WFT and WFE instructions in programming -- 9.3.1. When to use WFI -- 9.3.2. Using WFE -- 9.4. Developing low power applications -- 9.4.1. Reducing the active power -- 9.4.2. Reduction of active cycles -- 9.4.3. Sleep mode current reduction -- 9.5. The SysTick timer -- 9.5.1. Why have a SysTick timer -- 9.5.2. Operations of the SysTick timer -- 9.5.3. Using the SysTick timer -- 9.5.4. Other considerations -- 9.6. Self-reset -- 9.7. CPU ID base register -- 9.8. Configuration control register -- 9.8.1. Overview of CCR -- 9.8.2. Stkalign bit -- 9.8.3. Bfhfnmign bit -- 9.8.4. DIV_0_TRP bit -- 9.8.5. Unalign_Trp bit -- 9.8.6. Usersetmpend bit -- 9.8.7. Nonbasethrdena bit -- 9.9. Auxiliary control register -- 9.10. Co-processor access control register -- ch. 10 OS Support Features -- 10.1. Overview of OS support features -- 10.2. Shadowed stack pointer -- 10.3. SVC exception -- 10.4. PendSV exception -- 10.5. Context switching in action -- 10.6. Exclusive accesses and embedded OS -- ch. 11 Memory Protection Unit (MPU) -- 11.1. Overview of the MPU -- 11.1.1. About the MPU -- 11.1.2. Using the MPU -- 11.2. MPU registers -- 11.2.1. MPU type register -- 11.2.2. MPU control register -- 11.2.3. MPU region number register -- 11.2.4. MPU region base address register -- 11.2.5. MPU region base attribute and size register -- 11.2.6. MPU alias registers -- 11.3. Setting up the MPU -- 11.4. Memory barrier and MPU configuration -- 11.5. Using sub-region disable -- 11.5.1. Allow efficient memory separation -- 11.5.2. Reduce the total number of regions needed -- 11.6. Considerations when using MPU -- 11.6.1. Program code -- 11.6.2. Data memory -- 11.6.3. Peripherals -- 11.7. Other usages of the MPU -- 11.8.Comparing with the MPU in the Cortex®-M0+ processor -- ch. 12 Fault Exceptions and Fault Handling -- 12.1. Overview of fault exceptions -- 12.2. Causes of faults -- 12.2.1. Memory management (MemManage) faults -- 12.2.2. Bus faults -- 12.2.3. Usage</subfield></datafield><datafield tag="505" ind1="0" ind2=" "><subfield code="a">Note continued: 24.3.4. Pre-compiled object files and libraries -- 24.3.5. Optimization -- 24.4. Porting software between different Cortex®-M processors -- 24.4.1. Differences between different Cortex®-M processors -- 24.4.2. Required software changes -- 24.4.3. Embedded OS -- 24.4.4. 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| id | ZDB-4-EBA-ocn860906302 |
| illustrated | Illustrated |
| indexdate | 2024-10-25T16:21:38Z |
| institution | BVB |
| isbn | 9780124079182 0124079180 |
| language | English |
| oclc_num | 860906302 |
| open_access_boolean | |
| owner | MAIN |
| owner_facet | MAIN |
| physical | 1 online resource |
| psigel | ZDB-4-EBA |
| publishDate | 2013 |
| publishDateSearch | 2013 |
| publishDateSort | 2013 |
| publisher | Newnes, |
| record_format | marc |
| spelling | Yiu, Joseph, author. https://id.oclc.org/worldcat/entity/E39PCjqVXfxfPWVDJtPvp7fpKb http://id.loc.gov/authorities/names/nb2007027022 The definitive guide to ARM Cortex-M3 and Cortex-M4 processors / Joseph Yiu. Third edition. Amsterdam : Newnes, 2013. 1 online resource text txt rdacontent computer c rdamedia online resource cr rdacarrier Previous edition: 2010. Print version record. This book presents the background of the ARM architecture and outlines the features of the processors such as the instruction set, interrupt-handling and also demonstrates how to program and utilize the advanced features available such as the Memory Protection Unit (MPU). Chapters on getting started with IAR, Keil, gcc and CooCox CoIDE tools help beginners develop program codes. Coverage also includes the important areas of software development such as using the low power features, handling information input/output, mixed language projects with assembly and C, and other advanced topics. Two new chapters on DSP features and CMSIS-DSP software libraries, covering DSP fundamentals and how to write DSP software for the Cortex-M4 processor, including examples of using the CMSIS-DSP library, as well as useful information about the DSP capability of the Cortex-M4 processorA new chapter on the Cortex-M4 floating point unit and how to use itA new chapter on using embedded OS (based on CMSIS-RTOS), as well as details of processor features to support OS operationsTopics on software porting from other architecturesA full range of easy-to-understand examples, diagrams and quick reference appendices. Machine generated contents note: ch. 1 Introduction to ARM® Cortex®-M Processors -- 1.1. What are the ARM® Cortex®-M processors? -- 1.1.1. The Cortex®-M3 and Cortex-M4 processors -- 1.1.2. The Cortex®-M processor family -- 1.1.3. Differences between a processor and a microcontroller -- 1.1.4. ARM® and the microcontroller vendors -- 1.1.5. Selecting Cortex®-M3 and Cortex-M4 microcontrollers -- 1.2. Advantages of the Cortex®-M processors -- 1.2.1. Low power -- 1.2.2. Performance -- 1.2.3. Energy efficiency -- 1.2.4. Code density -- 1.2.5. Interrupts -- 1.2.6. Ease of use, C friendly -- 1.2.7. Scalability -- 1.2.8. Debug features -- 1.2.9. OS support -- 1.2.10. Versatile system features -- 1.2.11. Software portability and reusability -- 1.2.12. Choices (devices, tools, OS, etc.) -- 1.3. Applications of the ARM® Cortex®-M processors -- 1.4. Resources for using ARM® processors and ARM microcontrollers -- 1.4.1. What can you find on the ARM® website -- 1.4.2. Documentation from the microcontroller vendors -- 1.4.3. Documentation from tools vendors -- 1.4.4. Other resources -- 1.5. Background and history -- 1.5.1.A brief history of ARM® -- 1.5.2. ARM® processor evolution -- 1.5.3. Architecture versions and Thumb® ISA -- 1.5.4. Processor naming -- 1.5.5. About the ARM® ecosystem -- ch. 2 Introduction to Embedded Software Development -- 2.1. What are inside typical ARM® microcontrollers? -- 2.2. What you need to start -- 2.2.1. Development suites -- 2.2.2. Development boards -- 2.2.3. Debug adaptor -- 2.2.4. Software device driver -- 2.2.5. Examples -- 2.2.6. Documentation and other resources -- 2.2.7. Other equipment -- 2.3. Software development flow -- 2.4.Compiling your applications -- 2.5. Software flow -- 2.5.1. Polling -- 2.5.2. Interrupt driven -- 2.5.3. Multi-tasking systems -- 2.6. Data types in C programming -- 2.7. Inputs, outputs, and peripherals accesses -- 2.8. Microcontroller interfaces -- 2.9. The Cortex® microcontroller software interface standard (CMSIS) -- 2.9.1. Introduction of CMSIS -- 2.9.2. Areas of standardization in CMSIS-Core -- 2.9.3.Organization of CMSIS-Core -- 2.9.4. How do I use CMSIS-Core? -- 2.9.5. Benefits of CMSIS-Core -- 2.9.6. Various versions of CMSIS -- ch. 3 Technical Overview -- 3.1. General information about the Cortex®-M3 and Cortex-M4 processors -- 3.1.1. Processor type -- 3.1.2. Processor architecture -- 3.1.3. Instruction set -- 3.1.4. Block diagram -- 3.1.5. Memory system -- 3.1.6. Interrupt and exception support -- 3.2. Features of the Cortex®-M3 and Cortex-M4 processors -- 3.2.1. Performance -- 3.2.2. Code density -- 3.2.3. Low power -- 3.2.4. Memory system -- 3.2.5. Memory protection unit -- 3.2.6. Interrupt handling -- 3.2.7. OS support and system level features -- 3.2.8. Cortex®-M4 specific features -- 3.2.9. Ease of use -- 3.2.10. Debug support -- 3.2.11. Scalability -- 3.2.12.Compatibility -- ch. 4 Architecture -- 4.1. Introduction to the architecture -- 4.2. Programmer's model -- 4.2.1. Operation modes and states -- 4.2.2. Registers -- 4.2.3. Special registers -- 4.2.4. Floating point registers -- 4.3. Behavior of the application program status register (APSR) -- 4.3.1. Integer status flags -- 4.3.2.Q status flag -- 4.3.3. GE bits -- 4.4. Memory system -- 4.4.1. Memory system features -- 4.4.2. Memory map -- 4.4.3. Stack memory -- 4.4.4. Memory protection unit (MPU) -- 4.5. Exceptions and interrupts -- 4.5.1. What are exceptions? -- 4.5.2. Nested vectored interrupt controller (NVIC) -- 4.5.3. Vector table -- 4.5.4. Fault handling -- 4.6. System control block (SCB) -- 4.7. Debug -- 4.8. Reset and reset sequence -- Note continued: ch. 5 Instruction Set -- 5.1. Background to the instruction set in ARM® Cortex®-M processors -- 5.2.Comparison of the instruction set in ARM® Cortex®-M processors -- 5.3. Understanding the assembly language syntax -- 5.4. Use of a suffix in instructions -- 5.5. Unified assembly language (UAL) -- 5.6. Instruction set -- 5.6.1. Moving data within the processor -- 5.6.2. Memory access instructions -- 5.6.3. Arithmetic operations -- 5.6.4. Logic operations -- 5.6.5. Shift and rotate instructions -- 5.6.6. Data conversion operations (extend and reverse ordering) -- 5.6.7. Bit-field processing instructions -- 5.6.8.Compare and test -- 5.6.9. Program flow control -- 5.6.10. Saturation operations -- 5.6.11. Exception-related instructions -- 5.6.12. Sleep mode-related instructions -- 5.6.13. Memory barrier instructions -- 5.6.14. Other instructions -- 5.6.15. Unsupported instructions -- 5.7. Cortex®-M4-specific instructions -- 5.7.1. Overview of enhanced DSP extension in Cortex-M4 -- 5.7.2. SIMD and saturating instructions -- 5.7.3. Multiply and MAC instructions -- 5.7.4. Packing and unpacking -- 5.7.5. Floating point instructions -- 5.8. Barrel shifter -- 5.9. Accessing special instructions and special registers in programming -- 5.9.1. Overview -- 5.9.2. Intrinsic functions -- 5.9.3. Inline assembler and embedded assembler -- 5.9.4. Using other compiler-specific features -- 5.9.5. Access of special registers -- ch. 6 Memory System -- 6.1. Overview of memory system features -- 6.2. Memory map -- 6.3. Connecting the processor to memory and peripherals -- 6.4. Memory requirements -- 6.5. Memory endianness -- 6.6. Data alignment and unaligned data access support -- 6.7. Bit-band operations -- 6.7.1. Overview -- 6.7.2. Advantages of bit-band operations -- 6.7.3. Bit-band operation of different data sizes -- 6.7.4. Bit-band operations in C programs -- 6.8. Default memory access permissions -- 6.9. Memory access attributes -- 6.10. Exclusive accesses -- 6.11. Memory barriers -- 6.12. Memory system in a microcontroller -- ch. 7 Exceptions and Interrupts -- 7.1. Overview of exceptions and interrupts -- 7.2. Exception types -- 7.3. Overview of interrupt management -- 7.4. Definitions of priority -- 7.5. Vector table and vector table relocation -- 7.6. Interrupt inputs and pending behaviors -- 7.7. Exception sequence overview -- 7.7.1. Acceptance of exception request -- 7.7.2. Exception entrance sequence -- 7.7.3. Exception handler execution -- 7.7.4. Exception return -- 7.8. Details of NVIC registers for interrupt control -- 7.8.1. Summary -- 7.8.2. Interrupt enable registers -- 7.8.3. Interrupt set pending and clear pending -- 7.8.4. Active status -- 7.8.5. Priority level -- 7.8.6. Software trigger interrupt register -- 7.8.7. Interrupt controller type register -- 7.9. Details of SCB registers for exception and interrupt control -- 7.9.1. Summary of the SCB registers -- 7.9.2. Interrupt control and state register (ICSR) -- 7.9.3. Vector table offset register (VTOR) -- 7.9.4. Application interrupt and reset control register (AIRCR) -- 7.9.5. System handler priority registers (SCB-> SHP[0 to 11]) -- 7.9.6. System handler control and state register (SCB-> SHCSR) -- 7.10. Details of special registers for exception or interrupt masking -- 7.10.1. PRIMASK -- 7.10.2. FAULTMASK -- 7.10.3. BASEPRI -- 7.11. Example procedures in setting up interrupts -- 7.11.1. Simple cases -- 7.11.2. With vector table relocation -- 7.12. Software interrupts -- 7.13. Tips and hints -- Note continued: ch. 8 Exception Handling in Detail -- 8.1. Introduction -- 8.1.1. About this chapter -- 8.1.2. Exception handler in C -- 8.1.3. Stack frames -- 8.1.4. EXC_RETURN -- 8.2. Exception sequences -- 8.2.1. Exception entrance and stacking -- 8.2.2. Exception return and unstacking -- 8.3. Interrupt latency and exception handling optimization -- 8.3.1. What is interrupt latency? -- 8.3.2. Interrupts at multiple-cycle instructions -- 8.3.3. Tail chaining -- 8.3.4. Late arrival -- 8.3.5. Pop preemption -- 8.3.6. Lazy stacking -- ch. 9 Low Power and System Control Features -- 9.1. Low power designs -- 9.1.1. What does low power mean in microcontrollers? -- 9.1.2. Low power system requirements -- 9.1.3. Low power characteristics of the Cortex®-M3 and Cortex-M4 processors -- 9.2. Low power features -- 9.2.1. Sleep modes -- 9.2.2. System control register (SCR) -- 9.2.3. Entering sleep modes -- 9.2.4. Wake-up conditions -- 9.2.5. Sleep-on-Exit feature -- 9.2.6. Send event on pend (SEVONPEND) -- 9.2.7. Sleep extension/wake-up delay -- 9.2.8. Wake-up interrupt controller (WIC) -- 9.2.9. Event communication interface -- 9.3. Using WFT and WFE instructions in programming -- 9.3.1. When to use WFI -- 9.3.2. Using WFE -- 9.4. Developing low power applications -- 9.4.1. Reducing the active power -- 9.4.2. Reduction of active cycles -- 9.4.3. Sleep mode current reduction -- 9.5. The SysTick timer -- 9.5.1. Why have a SysTick timer -- 9.5.2. Operations of the SysTick timer -- 9.5.3. Using the SysTick timer -- 9.5.4. Other considerations -- 9.6. Self-reset -- 9.7. CPU ID base register -- 9.8. Configuration control register -- 9.8.1. Overview of CCR -- 9.8.2. Stkalign bit -- 9.8.3. Bfhfnmign bit -- 9.8.4. DIV_0_TRP bit -- 9.8.5. Unalign_Trp bit -- 9.8.6. Usersetmpend bit -- 9.8.7. Nonbasethrdena bit -- 9.9. Auxiliary control register -- 9.10. Co-processor access control register -- ch. 10 OS Support Features -- 10.1. Overview of OS support features -- 10.2. Shadowed stack pointer -- 10.3. SVC exception -- 10.4. PendSV exception -- 10.5. Context switching in action -- 10.6. Exclusive accesses and embedded OS -- ch. 11 Memory Protection Unit (MPU) -- 11.1. Overview of the MPU -- 11.1.1. About the MPU -- 11.1.2. Using the MPU -- 11.2. MPU registers -- 11.2.1. MPU type register -- 11.2.2. MPU control register -- 11.2.3. MPU region number register -- 11.2.4. MPU region base address register -- 11.2.5. MPU region base attribute and size register -- 11.2.6. MPU alias registers -- 11.3. Setting up the MPU -- 11.4. Memory barrier and MPU configuration -- 11.5. Using sub-region disable -- 11.5.1. Allow efficient memory separation -- 11.5.2. Reduce the total number of regions needed -- 11.6. Considerations when using MPU -- 11.6.1. Program code -- 11.6.2. Data memory -- 11.6.3. Peripherals -- 11.7. Other usages of the MPU -- 11.8.Comparing with the MPU in the Cortex®-M0+ processor -- ch. 12 Fault Exceptions and Fault Handling -- 12.1. Overview of fault exceptions -- 12.2. Causes of faults -- 12.2.1. Memory management (MemManage) faults -- 12.2.2. Bus faults -- 12.2.3. Usage Note continued: 24.3.4. Pre-compiled object files and libraries -- 24.3.5. Optimization -- 24.4. Porting software between different Cortex®-M processors -- 24.4.1. Differences between different Cortex®-M processors -- 24.4.2. Required software changes -- 24.4.3. Embedded OS -- 24.4.4. Creating portable program code for the Cortex®-M processors. Includes bibliographical references and index. Embedded computer systems. http://id.loc.gov/authorities/subjects/sh87006632 Microprocessors. http://id.loc.gov/authorities/subjects/sh85084898 Systèmes enfouis (Informatique) TECHNOLOGY & ENGINEERING Mechanical. bisacsh Embedded computer systems fast Microprocessors fast has work: The definitive guide to ARM® Cortex®-M3 and Cortex-M4 processors (Text) https://id.oclc.org/worldcat/entity/E39PCFQmcqrFkMpxFdbyYK4b7d https://id.oclc.org/worldcat/ontology/hasWork Print version: Yiu, Joseph. Definitive guide to ARM Cortex-M3 and Cortex-M4 processors. Third edition 9780124080829 (OCoLC)859555920 FWS01 ZDB-4-EBA FWS_PDA_EBA https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=516093 Volltext CBO01 ZDB-4-EBA FWS_PDA_EBA https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=516093 Volltext FWS01 ZDB-4-EBA FWS_PDA_EBA https://www.sciencedirect.com/science/book/9780124080829 Volltext CBO01 ZDB-4-EBA FWS_PDA_EBA https://www.sciencedirect.com/science/book/9780124080829 Volltext |
| spellingShingle | Yiu, Joseph The definitive guide to ARM Cortex-M3 and Cortex-M4 processors / Machine generated contents note: ch. 1 Introduction to ARM® Cortex®-M Processors -- 1.1. What are the ARM® Cortex®-M processors? -- 1.1.1. The Cortex®-M3 and Cortex-M4 processors -- 1.1.2. The Cortex®-M processor family -- 1.1.3. Differences between a processor and a microcontroller -- 1.1.4. ARM® and the microcontroller vendors -- 1.1.5. Selecting Cortex®-M3 and Cortex-M4 microcontrollers -- 1.2. Advantages of the Cortex®-M processors -- 1.2.1. Low power -- 1.2.2. Performance -- 1.2.3. Energy efficiency -- 1.2.4. Code density -- 1.2.5. Interrupts -- 1.2.6. Ease of use, C friendly -- 1.2.7. Scalability -- 1.2.8. Debug features -- 1.2.9. OS support -- 1.2.10. Versatile system features -- 1.2.11. Software portability and reusability -- 1.2.12. Choices (devices, tools, OS, etc.) -- 1.3. Applications of the ARM® Cortex®-M processors -- 1.4. Resources for using ARM® processors and ARM microcontrollers -- 1.4.1. What can you find on the ARM® website -- 1.4.2. Documentation from the microcontroller vendors -- 1.4.3. Documentation from tools vendors -- 1.4.4. Other resources -- 1.5. Background and history -- 1.5.1.A brief history of ARM® -- 1.5.2. ARM® processor evolution -- 1.5.3. Architecture versions and Thumb® ISA -- 1.5.4. Processor naming -- 1.5.5. About the ARM® ecosystem -- ch. 2 Introduction to Embedded Software Development -- 2.1. What are inside typical ARM® microcontrollers? -- 2.2. What you need to start -- 2.2.1. Development suites -- 2.2.2. Development boards -- 2.2.3. Debug adaptor -- 2.2.4. Software device driver -- 2.2.5. Examples -- 2.2.6. Documentation and other resources -- 2.2.7. Other equipment -- 2.3. Software development flow -- 2.4.Compiling your applications -- 2.5. Software flow -- 2.5.1. Polling -- 2.5.2. Interrupt driven -- 2.5.3. Multi-tasking systems -- 2.6. Data types in C programming -- 2.7. Inputs, outputs, and peripherals accesses -- 2.8. Microcontroller interfaces -- 2.9. The Cortex® microcontroller software interface standard (CMSIS) -- 2.9.1. Introduction of CMSIS -- 2.9.2. Areas of standardization in CMSIS-Core -- 2.9.3.Organization of CMSIS-Core -- 2.9.4. How do I use CMSIS-Core? -- 2.9.5. Benefits of CMSIS-Core -- 2.9.6. Various versions of CMSIS -- ch. 3 Technical Overview -- 3.1. General information about the Cortex®-M3 and Cortex-M4 processors -- 3.1.1. Processor type -- 3.1.2. Processor architecture -- 3.1.3. Instruction set -- 3.1.4. Block diagram -- 3.1.5. Memory system -- 3.1.6. Interrupt and exception support -- 3.2. Features of the Cortex®-M3 and Cortex-M4 processors -- 3.2.1. Performance -- 3.2.2. Code density -- 3.2.3. Low power -- 3.2.4. Memory system -- 3.2.5. Memory protection unit -- 3.2.6. Interrupt handling -- 3.2.7. OS support and system level features -- 3.2.8. Cortex®-M4 specific features -- 3.2.9. Ease of use -- 3.2.10. Debug support -- 3.2.11. Scalability -- 3.2.12.Compatibility -- ch. 4 Architecture -- 4.1. Introduction to the architecture -- 4.2. Programmer's model -- 4.2.1. Operation modes and states -- 4.2.2. Registers -- 4.2.3. Special registers -- 4.2.4. Floating point registers -- 4.3. Behavior of the application program status register (APSR) -- 4.3.1. Integer status flags -- 4.3.2.Q status flag -- 4.3.3. GE bits -- 4.4. Memory system -- 4.4.1. Memory system features -- 4.4.2. Memory map -- 4.4.3. Stack memory -- 4.4.4. Memory protection unit (MPU) -- 4.5. Exceptions and interrupts -- 4.5.1. What are exceptions? -- 4.5.2. Nested vectored interrupt controller (NVIC) -- 4.5.3. Vector table -- 4.5.4. Fault handling -- 4.6. System control block (SCB) -- 4.7. Debug -- 4.8. Reset and reset sequence -- Note continued: ch. 5 Instruction Set -- 5.1. Background to the instruction set in ARM® Cortex®-M processors -- 5.2.Comparison of the instruction set in ARM® Cortex®-M processors -- 5.3. Understanding the assembly language syntax -- 5.4. Use of a suffix in instructions -- 5.5. Unified assembly language (UAL) -- 5.6. Instruction set -- 5.6.1. Moving data within the processor -- 5.6.2. Memory access instructions -- 5.6.3. Arithmetic operations -- 5.6.4. Logic operations -- 5.6.5. Shift and rotate instructions -- 5.6.6. Data conversion operations (extend and reverse ordering) -- 5.6.7. Bit-field processing instructions -- 5.6.8.Compare and test -- 5.6.9. Program flow control -- 5.6.10. Saturation operations -- 5.6.11. Exception-related instructions -- 5.6.12. Sleep mode-related instructions -- 5.6.13. Memory barrier instructions -- 5.6.14. Other instructions -- 5.6.15. Unsupported instructions -- 5.7. Cortex®-M4-specific instructions -- 5.7.1. Overview of enhanced DSP extension in Cortex-M4 -- 5.7.2. SIMD and saturating instructions -- 5.7.3. Multiply and MAC instructions -- 5.7.4. Packing and unpacking -- 5.7.5. Floating point instructions -- 5.8. Barrel shifter -- 5.9. Accessing special instructions and special registers in programming -- 5.9.1. Overview -- 5.9.2. Intrinsic functions -- 5.9.3. Inline assembler and embedded assembler -- 5.9.4. Using other compiler-specific features -- 5.9.5. Access of special registers -- ch. 6 Memory System -- 6.1. Overview of memory system features -- 6.2. Memory map -- 6.3. Connecting the processor to memory and peripherals -- 6.4. Memory requirements -- 6.5. Memory endianness -- 6.6. Data alignment and unaligned data access support -- 6.7. Bit-band operations -- 6.7.1. Overview -- 6.7.2. Advantages of bit-band operations -- 6.7.3. Bit-band operation of different data sizes -- 6.7.4. Bit-band operations in C programs -- 6.8. Default memory access permissions -- 6.9. Memory access attributes -- 6.10. Exclusive accesses -- 6.11. Memory barriers -- 6.12. Memory system in a microcontroller -- ch. 7 Exceptions and Interrupts -- 7.1. Overview of exceptions and interrupts -- 7.2. Exception types -- 7.3. Overview of interrupt management -- 7.4. Definitions of priority -- 7.5. Vector table and vector table relocation -- 7.6. Interrupt inputs and pending behaviors -- 7.7. Exception sequence overview -- 7.7.1. Acceptance of exception request -- 7.7.2. Exception entrance sequence -- 7.7.3. Exception handler execution -- 7.7.4. Exception return -- 7.8. Details of NVIC registers for interrupt control -- 7.8.1. Summary -- 7.8.2. Interrupt enable registers -- 7.8.3. Interrupt set pending and clear pending -- 7.8.4. Active status -- 7.8.5. Priority level -- 7.8.6. Software trigger interrupt register -- 7.8.7. Interrupt controller type register -- 7.9. Details of SCB registers for exception and interrupt control -- 7.9.1. Summary of the SCB registers -- 7.9.2. Interrupt control and state register (ICSR) -- 7.9.3. Vector table offset register (VTOR) -- 7.9.4. Application interrupt and reset control register (AIRCR) -- 7.9.5. System handler priority registers (SCB-> SHP[0 to 11]) -- 7.9.6. System handler control and state register (SCB-> SHCSR) -- 7.10. Details of special registers for exception or interrupt masking -- 7.10.1. PRIMASK -- 7.10.2. FAULTMASK -- 7.10.3. BASEPRI -- 7.11. Example procedures in setting up interrupts -- 7.11.1. Simple cases -- 7.11.2. With vector table relocation -- 7.12. Software interrupts -- 7.13. Tips and hints -- Note continued: ch. 8 Exception Handling in Detail -- 8.1. Introduction -- 8.1.1. About this chapter -- 8.1.2. Exception handler in C -- 8.1.3. Stack frames -- 8.1.4. EXC_RETURN -- 8.2. Exception sequences -- 8.2.1. Exception entrance and stacking -- 8.2.2. Exception return and unstacking -- 8.3. Interrupt latency and exception handling optimization -- 8.3.1. What is interrupt latency? -- 8.3.2. Interrupts at multiple-cycle instructions -- 8.3.3. Tail chaining -- 8.3.4. Late arrival -- 8.3.5. Pop preemption -- 8.3.6. Lazy stacking -- ch. 9 Low Power and System Control Features -- 9.1. Low power designs -- 9.1.1. What does low power mean in microcontrollers? -- 9.1.2. Low power system requirements -- 9.1.3. Low power characteristics of the Cortex®-M3 and Cortex-M4 processors -- 9.2. Low power features -- 9.2.1. Sleep modes -- 9.2.2. System control register (SCR) -- 9.2.3. Entering sleep modes -- 9.2.4. Wake-up conditions -- 9.2.5. Sleep-on-Exit feature -- 9.2.6. Send event on pend (SEVONPEND) -- 9.2.7. Sleep extension/wake-up delay -- 9.2.8. Wake-up interrupt controller (WIC) -- 9.2.9. Event communication interface -- 9.3. Using WFT and WFE instructions in programming -- 9.3.1. When to use WFI -- 9.3.2. Using WFE -- 9.4. Developing low power applications -- 9.4.1. Reducing the active power -- 9.4.2. Reduction of active cycles -- 9.4.3. Sleep mode current reduction -- 9.5. The SysTick timer -- 9.5.1. Why have a SysTick timer -- 9.5.2. Operations of the SysTick timer -- 9.5.3. Using the SysTick timer -- 9.5.4. Other considerations -- 9.6. Self-reset -- 9.7. CPU ID base register -- 9.8. Configuration control register -- 9.8.1. Overview of CCR -- 9.8.2. Stkalign bit -- 9.8.3. Bfhfnmign bit -- 9.8.4. DIV_0_TRP bit -- 9.8.5. Unalign_Trp bit -- 9.8.6. Usersetmpend bit -- 9.8.7. Nonbasethrdena bit -- 9.9. Auxiliary control register -- 9.10. Co-processor access control register -- ch. 10 OS Support Features -- 10.1. Overview of OS support features -- 10.2. Shadowed stack pointer -- 10.3. SVC exception -- 10.4. PendSV exception -- 10.5. Context switching in action -- 10.6. Exclusive accesses and embedded OS -- ch. 11 Memory Protection Unit (MPU) -- 11.1. Overview of the MPU -- 11.1.1. About the MPU -- 11.1.2. Using the MPU -- 11.2. MPU registers -- 11.2.1. MPU type register -- 11.2.2. MPU control register -- 11.2.3. MPU region number register -- 11.2.4. MPU region base address register -- 11.2.5. MPU region base attribute and size register -- 11.2.6. MPU alias registers -- 11.3. Setting up the MPU -- 11.4. Memory barrier and MPU configuration -- 11.5. Using sub-region disable -- 11.5.1. Allow efficient memory separation -- 11.5.2. Reduce the total number of regions needed -- 11.6. Considerations when using MPU -- 11.6.1. Program code -- 11.6.2. Data memory -- 11.6.3. Peripherals -- 11.7. Other usages of the MPU -- 11.8.Comparing with the MPU in the Cortex®-M0+ processor -- ch. 12 Fault Exceptions and Fault Handling -- 12.1. Overview of fault exceptions -- 12.2. Causes of faults -- 12.2.1. Memory management (MemManage) faults -- 12.2.2. Bus faults -- 12.2.3. Usage Note continued: 24.3.4. Pre-compiled object files and libraries -- 24.3.5. Optimization -- 24.4. Porting software between different Cortex®-M processors -- 24.4.1. Differences between different Cortex®-M processors -- 24.4.2. Required software changes -- 24.4.3. Embedded OS -- 24.4.4. Creating portable program code for the Cortex®-M processors. Embedded computer systems. http://id.loc.gov/authorities/subjects/sh87006632 Microprocessors. http://id.loc.gov/authorities/subjects/sh85084898 Systèmes enfouis (Informatique) TECHNOLOGY & ENGINEERING Mechanical. bisacsh Embedded computer systems fast Microprocessors fast |
| subject_GND | http://id.loc.gov/authorities/subjects/sh87006632 http://id.loc.gov/authorities/subjects/sh85084898 |
| title | The definitive guide to ARM Cortex-M3 and Cortex-M4 processors / |
| title_auth | The definitive guide to ARM Cortex-M3 and Cortex-M4 processors / |
| title_exact_search | The definitive guide to ARM Cortex-M3 and Cortex-M4 processors / |
| title_full | The definitive guide to ARM Cortex-M3 and Cortex-M4 processors / Joseph Yiu. |
| title_fullStr | The definitive guide to ARM Cortex-M3 and Cortex-M4 processors / Joseph Yiu. |
| title_full_unstemmed | The definitive guide to ARM Cortex-M3 and Cortex-M4 processors / Joseph Yiu. |
| title_short | The definitive guide to ARM Cortex-M3 and Cortex-M4 processors / |
| title_sort | definitive guide to arm cortex m3 and cortex m4 processors |
| topic | Embedded computer systems. http://id.loc.gov/authorities/subjects/sh87006632 Microprocessors. http://id.loc.gov/authorities/subjects/sh85084898 Systèmes enfouis (Informatique) TECHNOLOGY & ENGINEERING Mechanical. bisacsh Embedded computer systems fast Microprocessors fast |
| topic_facet | Embedded computer systems. Microprocessors. Systèmes enfouis (Informatique) TECHNOLOGY & ENGINEERING Mechanical. Embedded computer systems Microprocessors |
| url | https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=516093 https://www.sciencedirect.com/science/book/9780124080829 |
| work_keys_str_mv | AT yiujoseph thedefinitiveguidetoarmcortexm3andcortexm4processors AT yiujoseph definitiveguidetoarmcortexm3andcortexm4processors |