Wafer-level testing and test during burn-in for integrated circuits /:
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston :
Artech House,
2010.
|
| Schriftenreihe: | Artech House integrated microsystems series.
|
| Schlagworte: | |
| Online-Zugang: | Volltext |
| Zusammenfassung: | Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions. |
| Beschreibung: | 1 online resource (xv, 198 pages) : illustrations |
| Bibliographie: | Includes bibliographical references and index. |
| ISBN: | 9781596939905 1596939907 |
Internformat
MARC
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| 100 | 1 | |a Bahukudumbi, Sudarshan. |e author. |4 aut |0 http://id.loc.gov/authorities/names/nb2010010627 | |
| 245 | 1 | 0 | |a Wafer-level testing and test during burn-in for integrated circuits / |c Sudarshan Bahukudumbi, Krishnendu Chakrabarty. |
| 260 | |a Boston : |b Artech House, |c 2010. | ||
| 300 | |a 1 online resource (xv, 198 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
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| 490 | 1 | |a Artech House integrated microsystems series | |
| 504 | |a Includes bibliographical references and index. | ||
| 520 | |a Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions. | ||
| 505 | 0 | |a Wafer-Level Test and Burn-In: Industry Practices and Trends -- Resource-Constrained Testing of Core-Based ScCs -- Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs -- Wafer-Level Test During Burn-In: Test Scheduling for Core-Based SoCs -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Ordering -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation. | |
| 588 | 0 | |a Print version record. | |
| 650 | 0 | |a Integrated circuits |x Testing. | |
| 650 | 0 | |a Integrated circuits |x Wafer-scale integration. |0 http://id.loc.gov/authorities/subjects/sh88004308 | |
| 650 | 0 | |a Semiconductors |x Testing. |0 http://id.loc.gov/authorities/subjects/sh85119917 | |
| 650 | 6 | |a Circuits intégrés |x Intégration sur la plaquette. | |
| 650 | 6 | |a Semi-conducteurs |x Essais. | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Microelectronics. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Digital. |2 bisacsh | |
| 650 | 7 | |a Integrated circuits |x Testing |2 fast | |
| 650 | 7 | |a Integrated circuits |x Wafer-scale integration |2 fast | |
| 650 | 7 | |a Semiconductors |x Testing |2 fast | |
| 700 | 1 | |a Chakrabarty, Krishnendu. |e author. |4 aut |0 http://id.loc.gov/authorities/names/n2002133223 | |
| 758 | |i has work: |a Wafer-level testing and test during burn-in for integrated circuits (Text) |1 https://id.oclc.org/worldcat/entity/E39PCGDQgTxKVHfCwr3TJKgBT3 |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
| 776 | 0 | 8 | |i Print version: |a Bahukudumbi, Sudarshan. |t Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty. |d Boston : Artech House, 2010 |z 1596939893 |w (DLC) 2010455090 |w (OCoLC)449516460 |
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Datensatz im Suchindex
| DE-BY-FWS_katkey | ZDB-4-EBA-ocn672293639 |
|---|---|
| _version_ | 1816881743911714817 |
| adam_text | |
| any_adam_object | |
| author | Bahukudumbi, Sudarshan Chakrabarty, Krishnendu |
| author_GND | http://id.loc.gov/authorities/names/nb2010010627 http://id.loc.gov/authorities/names/n2002133223 |
| author_facet | Bahukudumbi, Sudarshan Chakrabarty, Krishnendu |
| author_role | aut aut |
| author_sort | Bahukudumbi, Sudarshan |
| author_variant | s b sb k c kc |
| building | Verbundindex |
| bvnumber | localFWS |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874 .B35 2010 |
| callnumber-search | TK7874 .B35 2010 |
| callnumber-sort | TK 47874 B35 42010 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| collection | ZDB-4-EBA |
| contents | Wafer-Level Test and Burn-In: Industry Practices and Trends -- Resource-Constrained Testing of Core-Based ScCs -- Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs -- Wafer-Level Test During Burn-In: Test Scheduling for Core-Based SoCs -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Ordering -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation. |
| ctrlnum | (OCoLC)672293639 |
| dewey-full | 621.381 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.381 |
| dewey-search | 621.381 |
| dewey-sort | 3621.381 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | ZDB-4-EBA-ocn672293639 |
| illustrated | Illustrated |
| indexdate | 2024-11-27T13:17:35Z |
| institution | BVB |
| isbn | 9781596939905 1596939907 |
| language | English |
| oclc_num | 672293639 |
| open_access_boolean | |
| owner | MAIN DE-863 DE-BY-FWS |
| owner_facet | MAIN DE-863 DE-BY-FWS |
| physical | 1 online resource (xv, 198 pages) : illustrations |
| psigel | ZDB-4-EBA |
| publishDate | 2010 |
| publishDateSearch | 2010 |
| publishDateSort | 2010 |
| publisher | Artech House, |
| record_format | marc |
| series | Artech House integrated microsystems series. |
| series2 | Artech House integrated microsystems series |
| spelling | Bahukudumbi, Sudarshan. author. aut http://id.loc.gov/authorities/names/nb2010010627 Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty. Boston : Artech House, 2010. 1 online resource (xv, 198 pages) : illustrations text txt rdacontent computer c rdamedia online resource cr rdacarrier Artech House integrated microsystems series Includes bibliographical references and index. Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions. Wafer-Level Test and Burn-In: Industry Practices and Trends -- Resource-Constrained Testing of Core-Based ScCs -- Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs -- Wafer-Level Test During Burn-In: Test Scheduling for Core-Based SoCs -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Ordering -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation. Print version record. Integrated circuits Testing. Integrated circuits Wafer-scale integration. http://id.loc.gov/authorities/subjects/sh88004308 Semiconductors Testing. http://id.loc.gov/authorities/subjects/sh85119917 Circuits intégrés Intégration sur la plaquette. Semi-conducteurs Essais. TECHNOLOGY & ENGINEERING Electronics Microelectronics. bisacsh TECHNOLOGY & ENGINEERING Electronics Digital. bisacsh Integrated circuits Testing fast Integrated circuits Wafer-scale integration fast Semiconductors Testing fast Chakrabarty, Krishnendu. author. aut http://id.loc.gov/authorities/names/n2002133223 has work: Wafer-level testing and test during burn-in for integrated circuits (Text) https://id.oclc.org/worldcat/entity/E39PCGDQgTxKVHfCwr3TJKgBT3 https://id.oclc.org/worldcat/ontology/hasWork Print version: Bahukudumbi, Sudarshan. Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty. Boston : Artech House, 2010 1596939893 (DLC) 2010455090 (OCoLC)449516460 Artech House integrated microsystems series. http://id.loc.gov/authorities/names/nr2006021495 FWS01 ZDB-4-EBA FWS_PDA_EBA https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=339508 Volltext |
| spellingShingle | Bahukudumbi, Sudarshan Chakrabarty, Krishnendu Wafer-level testing and test during burn-in for integrated circuits / Artech House integrated microsystems series. Wafer-Level Test and Burn-In: Industry Practices and Trends -- Resource-Constrained Testing of Core-Based ScCs -- Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs -- Wafer-Level Test During Burn-In: Test Scheduling for Core-Based SoCs -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Ordering -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation. Integrated circuits Testing. Integrated circuits Wafer-scale integration. http://id.loc.gov/authorities/subjects/sh88004308 Semiconductors Testing. http://id.loc.gov/authorities/subjects/sh85119917 Circuits intégrés Intégration sur la plaquette. Semi-conducteurs Essais. TECHNOLOGY & ENGINEERING Electronics Microelectronics. bisacsh TECHNOLOGY & ENGINEERING Electronics Digital. bisacsh Integrated circuits Testing fast Integrated circuits Wafer-scale integration fast Semiconductors Testing fast |
| subject_GND | http://id.loc.gov/authorities/subjects/sh88004308 http://id.loc.gov/authorities/subjects/sh85119917 |
| title | Wafer-level testing and test during burn-in for integrated circuits / |
| title_auth | Wafer-level testing and test during burn-in for integrated circuits / |
| title_exact_search | Wafer-level testing and test during burn-in for integrated circuits / |
| title_full | Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty. |
| title_fullStr | Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty. |
| title_full_unstemmed | Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty. |
| title_short | Wafer-level testing and test during burn-in for integrated circuits / |
| title_sort | wafer level testing and test during burn in for integrated circuits |
| topic | Integrated circuits Testing. Integrated circuits Wafer-scale integration. http://id.loc.gov/authorities/subjects/sh88004308 Semiconductors Testing. http://id.loc.gov/authorities/subjects/sh85119917 Circuits intégrés Intégration sur la plaquette. Semi-conducteurs Essais. TECHNOLOGY & ENGINEERING Electronics Microelectronics. bisacsh TECHNOLOGY & ENGINEERING Electronics Digital. bisacsh Integrated circuits Testing fast Integrated circuits Wafer-scale integration fast Semiconductors Testing fast |
| topic_facet | Integrated circuits Testing. Integrated circuits Wafer-scale integration. Semiconductors Testing. Circuits intégrés Intégration sur la plaquette. Semi-conducteurs Essais. TECHNOLOGY & ENGINEERING Electronics Microelectronics. TECHNOLOGY & ENGINEERING Electronics Digital. Integrated circuits Testing Integrated circuits Wafer-scale integration Semiconductors Testing |
| url | https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=339508 |
| work_keys_str_mv | AT bahukudumbisudarshan waferleveltestingandtestduringburninforintegratedcircuits AT chakrabartykrishnendu waferleveltestingandtestduringburninforintegratedcircuits |