Microprocessor architecture :: from simple pipelines to chip multiprocessors /
This describes microprocessor architecture, from in-order short pipeline designs to out-of-order superscalars. The emphasis is on how things work at a black box and algorithmic level, with enough detail at the register transfer level to allow appreciation of how design features enhance performance a...
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| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
New York :
Cambridge University Press,
©2010.
|
| Schlagworte: | |
| Online-Zugang: | Volltext |
| Zusammenfassung: | This describes microprocessor architecture, from in-order short pipeline designs to out-of-order superscalars. The emphasis is on how things work at a black box and algorithmic level, with enough detail at the register transfer level to allow appreciation of how design features enhance performance as well as complexity. |
| Beschreibung: | 1 online resource : illustrations |
| Bibliographie: | Includes bibliographical references and index. |
| ISBN: | 9780511675461 0511675461 9780511672217 0511672217 9780511669361 0511669364 9780511739132 0511739133 9780511671463 0511671466 9786612486708 6612486708 9780511811258 051181125X |
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| 505 | 0 | |a Introduction -- The basics -- Superscalar processors -- Front-end : branch predictio, instruction fetching, and register renaming -- Back-end : instruction scheduling, memory access instructions, and clusters -- The cache hierarchy -- Multiprocessors -- Multithreading and (chip) multiprocessing -- Current limitations and future challenges. | |
| 588 | 0 | |a Print version record. | |
| 520 | 8 | |a This describes microprocessor architecture, from in-order short pipeline designs to out-of-order superscalars. The emphasis is on how things work at a black box and algorithmic level, with enough detail at the register transfer level to allow appreciation of how design features enhance performance as well as complexity. | |
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| contents | Introduction -- The basics -- Superscalar processors -- Front-end : branch predictio, instruction fetching, and register renaming -- Back-end : instruction scheduling, memory access instructions, and clusters -- The cache hierarchy -- Multiprocessors -- Multithreading and (chip) multiprocessing -- Current limitations and future challenges. |
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| spelling | Baer, Jean-Loup. http://id.loc.gov/authorities/names/n78052626 Microprocessor architecture : from simple pipelines to chip multiprocessors / Jean-Loup Baer. New York : Cambridge University Press, ©2010. 1 online resource : illustrations text txt rdacontent computer c rdamedia online resource cr rdacarrier Includes bibliographical references and index. Introduction -- The basics -- Superscalar processors -- Front-end : branch predictio, instruction fetching, and register renaming -- Back-end : instruction scheduling, memory access instructions, and clusters -- The cache hierarchy -- Multiprocessors -- Multithreading and (chip) multiprocessing -- Current limitations and future challenges. Print version record. This describes microprocessor architecture, from in-order short pipeline designs to out-of-order superscalars. The emphasis is on how things work at a black box and algorithmic level, with enough detail at the register transfer level to allow appreciation of how design features enhance performance as well as complexity. Microprocessors. http://id.loc.gov/authorities/subjects/sh85084898 Computer architecture. http://id.loc.gov/authorities/subjects/sh85029479 Ordinateurs Architecture. COMPUTERS Systems Architecture General. bisacsh Computer architecture fast Microprocessors fast Electronic books. has work: Microprocessor architecture (Text) https://id.oclc.org/worldcat/entity/E39PCFKXJMjwPbXwwrYwJ97gDq https://id.oclc.org/worldcat/ontology/hasWork Print version: Baer, Jean-Loup. Microprocessor architecture. New York : Cambridge University Press, 2010 9780521769921 (DLC) 2009025686 (OCoLC)421947809 FWS01 ZDB-4-EBA FWS_PDA_EBA https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=312518 Volltext |
| spellingShingle | Baer, Jean-Loup Microprocessor architecture : from simple pipelines to chip multiprocessors / Introduction -- The basics -- Superscalar processors -- Front-end : branch predictio, instruction fetching, and register renaming -- Back-end : instruction scheduling, memory access instructions, and clusters -- The cache hierarchy -- Multiprocessors -- Multithreading and (chip) multiprocessing -- Current limitations and future challenges. Microprocessors. http://id.loc.gov/authorities/subjects/sh85084898 Computer architecture. http://id.loc.gov/authorities/subjects/sh85029479 Ordinateurs Architecture. COMPUTERS Systems Architecture General. bisacsh Computer architecture fast Microprocessors fast |
| subject_GND | http://id.loc.gov/authorities/subjects/sh85084898 http://id.loc.gov/authorities/subjects/sh85029479 |
| title | Microprocessor architecture : from simple pipelines to chip multiprocessors / |
| title_auth | Microprocessor architecture : from simple pipelines to chip multiprocessors / |
| title_exact_search | Microprocessor architecture : from simple pipelines to chip multiprocessors / |
| title_full | Microprocessor architecture : from simple pipelines to chip multiprocessors / Jean-Loup Baer. |
| title_fullStr | Microprocessor architecture : from simple pipelines to chip multiprocessors / Jean-Loup Baer. |
| title_full_unstemmed | Microprocessor architecture : from simple pipelines to chip multiprocessors / Jean-Loup Baer. |
| title_short | Microprocessor architecture : |
| title_sort | microprocessor architecture from simple pipelines to chip multiprocessors |
| title_sub | from simple pipelines to chip multiprocessors / |
| topic | Microprocessors. http://id.loc.gov/authorities/subjects/sh85084898 Computer architecture. http://id.loc.gov/authorities/subjects/sh85029479 Ordinateurs Architecture. COMPUTERS Systems Architecture General. bisacsh Computer architecture fast Microprocessors fast |
| topic_facet | Microprocessors. Computer architecture. Ordinateurs Architecture. COMPUTERS Systems Architecture General. Computer architecture Microprocessors Electronic books. |
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