Hybrid CMOS single-electron-transistor device and circuit design /:
"This cutting-edge resource shows engineers how to take advantage of the low-power consumption and enhanced functionality of SETs (single-electron transistors) along with the high-speed driving and voltage gain of CMOS technology. The book provides the conceptual framework for CMOS-SET hybrid c...
Gespeichert in:
1. Verfasser: | |
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Weitere Verfasser: | |
Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Boston, Mass. ; London :
Artech House,
©2006.
|
Schriftenreihe: | Artech House integrated microsystems series.
|
Schlagworte: | |
Online-Zugang: | Volltext |
Zusammenfassung: | "This cutting-edge resource shows engineers how to take advantage of the low-power consumption and enhanced functionality of SETs (single-electron transistors) along with the high-speed driving and voltage gain of CMOS technology. The book provides the conceptual framework for CMOS-SET hybrid circuit design. Supported with over 180 illustrations and packaged with a CD-ROM of practical supplementary material, the book discusses."--Jacket |
Beschreibung: | 1 online resource (xvii, 218 pages) : illustrations |
Format: | Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002. |
Bibliographie: | Includes bibliographical references and index. |
ISBN: | 9781596930704 1596930705 |
Internformat
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588 | 0 | |a Print version record. | |
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533 | |a Electronic reproduction. |b [Place of publication not identified] : |c HathiTrust Digital Library, |d 2010. |5 MiAaHDL | ||
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583 | 1 | |a digitized |c 2010 |h HathiTrust Digital Library |l committed to preserve |2 pda |5 MiAaHDL | |
505 | 0 | 0 | |g Machine generated contents note: |g 1. |t Introduction : CMOS scaling and single electronics -- |g 2. |t Compact modeling of SETs -- |g 3. |t Single-electron transistor logic -- |g 4. |t Hybridization of CMOS and SET -- |g 5. |t Few electron multiple valued logic and memory design -- |g 6. |t Fabrication of SETs and compatibility with silicon CMOS -- |g App. |t A Gibbs free energy and development of MIB model. |
520 | |a "This cutting-edge resource shows engineers how to take advantage of the low-power consumption and enhanced functionality of SETs (single-electron transistors) along with the high-speed driving and voltage gain of CMOS technology. The book provides the conceptual framework for CMOS-SET hybrid circuit design. Supported with over 180 illustrations and packaged with a CD-ROM of practical supplementary material, the book discusses."--Jacket | ||
650 | 0 | |a Metal oxide semiconductors, Complementary. |0 http://id.loc.gov/authorities/subjects/sh85084067 | |
650 | 0 | |a Integrated circuits |x Design and construction. |0 http://id.loc.gov/authorities/subjects/sh85067118 | |
650 | 6 | |a MOS complémentaires. | |
650 | 6 | |a Circuits intégrés |x Conception et construction. | |
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758 | |i has work: |a Hybrid CMOS single-electron-transistor device and circuit design (Text) |1 https://id.oclc.org/worldcat/entity/E39PCFXP4mg8FQqf7tkFX9qPcP |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
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DE-BY-FWS_katkey | ZDB-4-EBA-ocn228291428 |
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adam_text | |
any_adam_object | |
author | Mahapatra, Santanu |
author2 | Ionescu, Adrian M. |
author2_role | |
author2_variant | a m i am ami |
author_GND | http://id.loc.gov/authorities/names/nb2006025560 http://id.loc.gov/authorities/names/n2003015058 |
author_facet | Mahapatra, Santanu Ionescu, Adrian M. |
author_role | |
author_sort | Mahapatra, Santanu |
author_variant | s m sm |
building | Verbundindex |
bvnumber | localFWS |
callnumber-first | T - Technology |
callnumber-label | TK7871 |
callnumber-raw | TK7871.99.M44 M247 2006eb |
callnumber-search | TK7871.99.M44 M247 2006eb |
callnumber-sort | TK 47871.99 M44 M247 42006EB |
callnumber-subject | TK - Electrical and Nuclear Engineering |
collection | ZDB-4-EBA |
contents | Introduction : CMOS scaling and single electronics -- Compact modeling of SETs -- Single-electron transistor logic -- Hybridization of CMOS and SET -- Few electron multiple valued logic and memory design -- Fabrication of SETs and compatibility with silicon CMOS -- A Gibbs free energy and development of MIB model. |
ctrlnum | (OCoLC)228291428 |
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dewey-ones | 621 - Applied physics |
dewey-raw | 621.39732 |
dewey-search | 621.39732 |
dewey-sort | 3621.39732 |
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discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
format | Electronic eBook |
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id | ZDB-4-EBA-ocn228291428 |
illustrated | Illustrated |
indexdate | 2024-11-27T13:16:21Z |
institution | BVB |
isbn | 9781596930704 1596930705 |
language | English |
oclc_num | 228291428 |
open_access_boolean | |
owner | MAIN DE-863 DE-BY-FWS |
owner_facet | MAIN DE-863 DE-BY-FWS |
physical | 1 online resource (xvii, 218 pages) : illustrations |
psigel | ZDB-4-EBA |
publishDate | 2006 |
publishDateSearch | 2006 |
publishDateSort | 2006 |
publisher | Artech House, |
record_format | marc |
series | Artech House integrated microsystems series. |
series2 | Artech House integrated microsystems series |
spelling | Mahapatra, Santanu. http://id.loc.gov/authorities/names/nb2006025560 Hybrid CMOS single-electron-transistor device and circuit design / Santanu Mahapatra, Adrian Mihai Ionescu. Boston, Mass. ; London : Artech House, ©2006. 1 online resource (xvii, 218 pages) : illustrations text txt rdacontent computer c rdamedia online resource cr rdacarrier data file Artech House integrated microsystems series Includes bibliographical references and index. Print version record. Use copy Restrictions unspecified star MiAaHDL Electronic reproduction. [Place of publication not identified] : HathiTrust Digital Library, 2010. MiAaHDL Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002. http://purl.oclc.org/DLF/benchrepro0212 MiAaHDL digitized 2010 HathiTrust Digital Library committed to preserve pda MiAaHDL Machine generated contents note: 1. Introduction : CMOS scaling and single electronics -- 2. Compact modeling of SETs -- 3. Single-electron transistor logic -- 4. Hybridization of CMOS and SET -- 5. Few electron multiple valued logic and memory design -- 6. Fabrication of SETs and compatibility with silicon CMOS -- App. A Gibbs free energy and development of MIB model. "This cutting-edge resource shows engineers how to take advantage of the low-power consumption and enhanced functionality of SETs (single-electron transistors) along with the high-speed driving and voltage gain of CMOS technology. The book provides the conceptual framework for CMOS-SET hybrid circuit design. Supported with over 180 illustrations and packaged with a CD-ROM of practical supplementary material, the book discusses."--Jacket Metal oxide semiconductors, Complementary. http://id.loc.gov/authorities/subjects/sh85084067 Integrated circuits Design and construction. http://id.loc.gov/authorities/subjects/sh85067118 MOS complémentaires. Circuits intégrés Conception et construction. COMPUTERS Machine Theory. bisacsh COMPUTERS Computer Engineering. bisacsh COMPUTERS Hardware General. bisacsh Integrated circuits Design and construction fast Metal oxide semiconductors, Complementary fast Ionescu, Adrian M. http://id.loc.gov/authorities/names/n2003015058 has work: Hybrid CMOS single-electron-transistor device and circuit design (Text) https://id.oclc.org/worldcat/entity/E39PCFXP4mg8FQqf7tkFX9qPcP https://id.oclc.org/worldcat/ontology/hasWork Print version: Mahapatra, Santanu. Hybrid CMOS single-electron-transistor device and circuit design. Boston, Mass. ; London : Artech House, ©2006 9781596930704 1596930705 (DLC) 2007270097 (OCoLC)76797690 Artech House integrated microsystems series. http://id.loc.gov/authorities/names/nr2006021495 FWS01 ZDB-4-EBA FWS_PDA_EBA https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=225172 Volltext |
spellingShingle | Mahapatra, Santanu Hybrid CMOS single-electron-transistor device and circuit design / Artech House integrated microsystems series. Introduction : CMOS scaling and single electronics -- Compact modeling of SETs -- Single-electron transistor logic -- Hybridization of CMOS and SET -- Few electron multiple valued logic and memory design -- Fabrication of SETs and compatibility with silicon CMOS -- A Gibbs free energy and development of MIB model. Metal oxide semiconductors, Complementary. http://id.loc.gov/authorities/subjects/sh85084067 Integrated circuits Design and construction. http://id.loc.gov/authorities/subjects/sh85067118 MOS complémentaires. Circuits intégrés Conception et construction. COMPUTERS Machine Theory. bisacsh COMPUTERS Computer Engineering. bisacsh COMPUTERS Hardware General. bisacsh Integrated circuits Design and construction fast Metal oxide semiconductors, Complementary fast |
subject_GND | http://id.loc.gov/authorities/subjects/sh85084067 http://id.loc.gov/authorities/subjects/sh85067118 |
title | Hybrid CMOS single-electron-transistor device and circuit design / |
title_alt | Introduction : CMOS scaling and single electronics -- Compact modeling of SETs -- Single-electron transistor logic -- Hybridization of CMOS and SET -- Few electron multiple valued logic and memory design -- Fabrication of SETs and compatibility with silicon CMOS -- A Gibbs free energy and development of MIB model. |
title_auth | Hybrid CMOS single-electron-transistor device and circuit design / |
title_exact_search | Hybrid CMOS single-electron-transistor device and circuit design / |
title_full | Hybrid CMOS single-electron-transistor device and circuit design / Santanu Mahapatra, Adrian Mihai Ionescu. |
title_fullStr | Hybrid CMOS single-electron-transistor device and circuit design / Santanu Mahapatra, Adrian Mihai Ionescu. |
title_full_unstemmed | Hybrid CMOS single-electron-transistor device and circuit design / Santanu Mahapatra, Adrian Mihai Ionescu. |
title_short | Hybrid CMOS single-electron-transistor device and circuit design / |
title_sort | hybrid cmos single electron transistor device and circuit design |
topic | Metal oxide semiconductors, Complementary. http://id.loc.gov/authorities/subjects/sh85084067 Integrated circuits Design and construction. http://id.loc.gov/authorities/subjects/sh85067118 MOS complémentaires. Circuits intégrés Conception et construction. COMPUTERS Machine Theory. bisacsh COMPUTERS Computer Engineering. bisacsh COMPUTERS Hardware General. bisacsh Integrated circuits Design and construction fast Metal oxide semiconductors, Complementary fast |
topic_facet | Metal oxide semiconductors, Complementary. Integrated circuits Design and construction. MOS complémentaires. Circuits intégrés Conception et construction. COMPUTERS Machine Theory. COMPUTERS Computer Engineering. COMPUTERS Hardware General. Integrated circuits Design and construction Metal oxide semiconductors, Complementary |
url | https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=225172 |
work_keys_str_mv | AT mahapatrasantanu hybridcmossingleelectrontransistordeviceandcircuitdesign AT ionescuadrianm hybridcmossingleelectrontransistordeviceandcircuitdesign |