Verification techniques for system-level design /:
This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as...
Gespeichert in:
| 1. Verfasser: | |
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| Weitere Verfasser: | , |
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam ; Boston :
Morgan Kaufmann Publishers,
©2008.
|
| Schriftenreihe: | Morgan Kaufmann series in systems on silicon.
|
| Schlagworte: | |
| Online-Zugang: | Volltext Volltext |
| Zusammenfassung: | This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology. Printbegrænsninger: Der kan printes kapitelvis. |
| Beschreibung: | 1 online resource (viii, 240 pages) : illustrations |
| Bibliographie: | Includes bibliographical references and index. |
| ISBN: | 9780080553139 0080553133 1281049646 9781281049643 9786611049645 6611049649 |
Internformat
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| 245 | 1 | 0 | |a Verification techniques for system-level design / |c Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad. |
| 260 | |a Amsterdam ; |a Boston : |b Morgan Kaufmann Publishers, |c ©2008. | ||
| 300 | |a 1 online resource (viii, 240 pages) : |b illustrations | ||
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| 490 | 1 | |a The Morgan Kaufmann series in systems on silicon | |
| 504 | |a Includes bibliographical references and index. | ||
| 520 | 8 | |a This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology. | |
| 520 | 8 | |a Printbegrænsninger: Der kan printes kapitelvis. | |
| 505 | 0 | |a 1. Introduction -- 2. Higher-Level Design Methodology and Associated Verification Problems -- 3. Basic Technology for Formal Verification -- 4. Verification Algorithms for FSM Models -- 5. Static Checking of Higher-Level Design Descriptions -- 6. Equivalence Checking on Higher-Level Design Descriptions -- 7. Model Checking on Higher-Level Design Descriptions -- 8. Simulation-Based Verification Techniques for System-Level Designs -- 9. Conclusion. | |
| 588 | 0 | |a Print version record. | |
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| 650 | 0 | |a Formal methods (Computer science) |0 http://id.loc.gov/authorities/subjects/sh99003622 | |
| 650 | 6 | |a Circuits intégrés |x Vérification. | |
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| 655 | 7 | |a dissertations. |2 aat | |
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| 655 | 7 | |a Thèses et écrits académiques. |2 rvmgf | |
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| 700 | 1 | |a Prasad, Mukul. |0 http://id.loc.gov/authorities/names/n2007047206 | |
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Datensatz im Suchindex
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| adam_text | |
| any_adam_object | |
| author | Fujita, Masahiro, 1956- |
| author2 | Ghosh, Indradeep, 1970- Prasad, Mukul |
| author2_role | |
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| author_GND | http://id.loc.gov/authorities/names/n96023352 http://id.loc.gov/authorities/names/nr98015919 http://id.loc.gov/authorities/names/n2007047206 |
| author_facet | Fujita, Masahiro, 1956- Ghosh, Indradeep, 1970- Prasad, Mukul |
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| collection | ZDB-4-EBA |
| contents | 1. Introduction -- 2. Higher-Level Design Methodology and Associated Verification Problems -- 3. Basic Technology for Formal Verification -- 4. Verification Algorithms for FSM Models -- 5. Static Checking of Higher-Level Design Descriptions -- 6. Equivalence Checking on Higher-Level Design Descriptions -- 7. Model Checking on Higher-Level Design Descriptions -- 8. Simulation-Based Verification Techniques for System-Level Designs -- 9. Conclusion. |
| ctrlnum | (OCoLC)182548558 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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ind2=" "><subfield code="a">This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. 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| genre_facet | dissertations. Academic theses Academic theses. Thèses et écrits académiques. |
| id | ZDB-4-EBA-ocn182548558 |
| illustrated | Illustrated |
| indexdate | 2024-11-27T13:16:12Z |
| institution | BVB |
| isbn | 9780080553139 0080553133 1281049646 9781281049643 9786611049645 6611049649 |
| language | English |
| lccn | 2007028038 |
| oclc_num | 182548558 |
| open_access_boolean | |
| owner | MAIN DE-863 DE-BY-FWS |
| owner_facet | MAIN DE-863 DE-BY-FWS |
| physical | 1 online resource (viii, 240 pages) : illustrations |
| psigel | ZDB-4-EBA |
| publishDate | 2008 |
| publishDateSearch | 2008 |
| publishDateSort | 2008 |
| publisher | Morgan Kaufmann Publishers, |
| record_format | marc |
| series | Morgan Kaufmann series in systems on silicon. |
| series2 | The Morgan Kaufmann series in systems on silicon |
| spelling | Fujita, Masahiro, 1956- https://id.oclc.org/worldcat/entity/E39PCjMyKbwXQVQhk9wQbFWQjd http://id.loc.gov/authorities/names/n96023352 Verification techniques for system-level design / Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad. Amsterdam ; Boston : Morgan Kaufmann Publishers, ©2008. 1 online resource (viii, 240 pages) : illustrations text txt rdacontent computer c rdamedia online resource cr rdacarrier The Morgan Kaufmann series in systems on silicon Includes bibliographical references and index. This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology. Printbegrænsninger: Der kan printes kapitelvis. 1. Introduction -- 2. Higher-Level Design Methodology and Associated Verification Problems -- 3. Basic Technology for Formal Verification -- 4. Verification Algorithms for FSM Models -- 5. Static Checking of Higher-Level Design Descriptions -- 6. Equivalence Checking on Higher-Level Design Descriptions -- 7. Model Checking on Higher-Level Design Descriptions -- 8. Simulation-Based Verification Techniques for System-Level Designs -- 9. Conclusion. Print version record. English. Systems on a chip Testing. Integrated circuits Verification. http://id.loc.gov/authorities/subjects/sh93005422 Formal methods (Computer science) http://id.loc.gov/authorities/subjects/sh99003622 Circuits intégrés Vérification. Méthodes formelles (Informatique) TECHNOLOGY & ENGINEERING Electronics Circuits Integrated. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits General. bisacsh Systems on a chip Testing. blmlsh Integrated circuits Verification. blmlsh Formal methods (Computer science) blmlsh Formal methods (Computer science) fast Integrated circuits Verification fast dissertations. aat Academic theses fast Academic theses. lcgft http://id.loc.gov/authorities/genreForms/gf2014026039 Thèses et écrits académiques. rvmgf Ghosh, Indradeep, 1970- https://id.oclc.org/worldcat/entity/E39PCjrfCggcm7b3YgGFXHMTMd http://id.loc.gov/authorities/names/nr98015919 Prasad, Mukul. http://id.loc.gov/authorities/names/n2007047206 has work: Verification techniques for system-level design (Text) https://id.oclc.org/worldcat/entity/E39PCG7DGGQPHGyqGCXc443WWC https://id.oclc.org/worldcat/ontology/hasWork Print version: Fujita, Masahiro, 1956- Verification techniques for system-level design. Amsterdam ; Boston : Morgan Kaufmann Publishers, ©2008 9780123706164 0123706165 (DLC) 2007028038 (OCoLC)155126176 Morgan Kaufmann series in systems on silicon. http://id.loc.gov/authorities/names/n2001146727 FWS01 ZDB-4-EBA FWS_PDA_EBA https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=210385 Volltext FWS01 ZDB-4-EBA FWS_PDA_EBA https://www.sciencedirect.com/science/book/9780123706164 Volltext |
| spellingShingle | Fujita, Masahiro, 1956- Verification techniques for system-level design / Morgan Kaufmann series in systems on silicon. 1. Introduction -- 2. Higher-Level Design Methodology and Associated Verification Problems -- 3. Basic Technology for Formal Verification -- 4. Verification Algorithms for FSM Models -- 5. Static Checking of Higher-Level Design Descriptions -- 6. Equivalence Checking on Higher-Level Design Descriptions -- 7. Model Checking on Higher-Level Design Descriptions -- 8. Simulation-Based Verification Techniques for System-Level Designs -- 9. Conclusion. Systems on a chip Testing. Integrated circuits Verification. http://id.loc.gov/authorities/subjects/sh93005422 Formal methods (Computer science) http://id.loc.gov/authorities/subjects/sh99003622 Circuits intégrés Vérification. Méthodes formelles (Informatique) TECHNOLOGY & ENGINEERING Electronics Circuits Integrated. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits General. bisacsh Systems on a chip Testing. blmlsh Integrated circuits Verification. blmlsh Formal methods (Computer science) blmlsh Formal methods (Computer science) fast Integrated circuits Verification fast |
| subject_GND | http://id.loc.gov/authorities/subjects/sh93005422 http://id.loc.gov/authorities/subjects/sh99003622 http://id.loc.gov/authorities/genreForms/gf2014026039 |
| title | Verification techniques for system-level design / |
| title_auth | Verification techniques for system-level design / |
| title_exact_search | Verification techniques for system-level design / |
| title_full | Verification techniques for system-level design / Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad. |
| title_fullStr | Verification techniques for system-level design / Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad. |
| title_full_unstemmed | Verification techniques for system-level design / Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad. |
| title_short | Verification techniques for system-level design / |
| title_sort | verification techniques for system level design |
| topic | Systems on a chip Testing. Integrated circuits Verification. http://id.loc.gov/authorities/subjects/sh93005422 Formal methods (Computer science) http://id.loc.gov/authorities/subjects/sh99003622 Circuits intégrés Vérification. Méthodes formelles (Informatique) TECHNOLOGY & ENGINEERING Electronics Circuits Integrated. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits General. bisacsh Systems on a chip Testing. blmlsh Integrated circuits Verification. blmlsh Formal methods (Computer science) blmlsh Formal methods (Computer science) fast Integrated circuits Verification fast |
| topic_facet | Systems on a chip Testing. Integrated circuits Verification. Formal methods (Computer science) Circuits intégrés Vérification. Méthodes formelles (Informatique) TECHNOLOGY & ENGINEERING Electronics Circuits Integrated. TECHNOLOGY & ENGINEERING Electronics Circuits General. Integrated circuits Verification dissertations. Academic theses Academic theses. Thèses et écrits académiques. |
| url | https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=210385 https://www.sciencedirect.com/science/book/9780123706164 |
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