Verfügbarkeit: Design recipes for FPGAs /

Design recipes for FPGAs /:

A rich treasure chest of design techniques and templates for solving practical, every-day problems using FPGAs.

Gespeichert in:

Bibliographische Detailangaben
1. Verfasser:	Wilson, Peter R. (Peter Robert), 1939-
Format:	Elektronisch E-Book
Sprache:	English
Veröffentlicht:	Amsterdam ; Boston ; London : Newnes, 2007.
Schlagworte:	Field programmable gate arrays > Design and construction. Gate array circuits. Circuits prédiffusés. TECHNOLOGY & ENGINEERING > Electronics > Circuits > VLSI & ULSI. TECHNOLOGY & ENGINEERING > Electronics > Circuits > Logic. COMPUTERS > Logic Design. Field programmable gate arrays > Design and construction dissertations. Academic theses Academic theses. Thèses et écrits académiques.
Online-Zugang:	Volltext Volltext
Zusammenfassung:	A rich treasure chest of design techniques and templates for solving practical, every-day problems using FPGAs.
Beschreibung:	1 online resource (xxii, 289 pages :)
Bibliographie:	Includes bibliographical references (pages 284-285) and index.
ISBN:	9780080548425 0080548423

Internformat

MARC


LEADER	00000cam a2200000 a 4500
001	ZDB-4-EBA-ocn173502373
003	OCoLC
005	20240705115654.0
006	m o d
007	cr cnu---unuuu
008	070929s2007 ne a ob 001 0 eng d
040			\|a N$T \|b eng \|e pn \|c N$T \|d OCLCQ \|d YDXCP \|d OCLCQ \|d IDEBK \|d E7B \|d OCLCQ \|d MERUC \|d OCLCQ \|d OCLCF \|d ZI0 \|d OCLCQ \|d OPELS \|d BAKER \|d UMI \|d OCLCQ \|d COO \|d LOA \|d DEBBG \|d COCUF \|d AGLDB \|d STF \|d MOR \|d PIFAG \|d OCLCQ \|d JBG \|d U3W \|d WRM \|d D6H \|d OCLCQ \|d VTS \|d CEF \|d INT \|d VT2 \|d OCLCQ \|d LEAUB \|d M8D \|d HS0 \|d UWK \|d UKBTH \|d UKCRE \|d UKSSU \|d OCLCQ \|d OCLCO \|d OCLCQ \|d KSU \|d OCLCQ \|d OCLCO \|d OCLCL \|d EZC \|d QGK \|d OCLCO
019			\|a 162591610 \|a 648316386 \|a 811269691 \|a 931874288 \|a 961695269 \|a 962729704 \|a 966200456 \|a 984784290 \|a 988441831 \|a 992027249 \|a 1034916821 \|a 1037739629 \|a 1038605848 \|a 1055348826 \|a 1081216825 \|a 1109116352 \|a 1110363412 \|a 1113567517 \|a 1152993080 \|a 1154865067 \|a 1159645743 \|a 1162032659 \|a 1192348045 \|a 1227634132 \|a 1228619455 \|a 1434172865
020			\|a 9780080548425 \|q (electronic bk.)
020			\|a 0080548423 \|q (electronic bk.)
020			\|z 9780750668453 \|q (pbk.)
020			\|z 0750668458 \|q (pbk.)
035			\|a (OCoLC)173502373 \|z (OCoLC)162591610 \|z (OCoLC)648316386 \|z (OCoLC)811269691 \|z (OCoLC)931874288 \|z (OCoLC)961695269 \|z (OCoLC)962729704 \|z (OCoLC)966200456 \|z (OCoLC)984784290 \|z (OCoLC)988441831 \|z (OCoLC)992027249 \|z (OCoLC)1034916821 \|z (OCoLC)1037739629 \|z (OCoLC)1038605848 \|z (OCoLC)1055348826 \|z (OCoLC)1081216825 \|z (OCoLC)1109116352 \|z (OCoLC)1110363412 \|z (OCoLC)1113567517 \|z (OCoLC)1152993080 \|z (OCoLC)1154865067 \|z (OCoLC)1159645743 \|z (OCoLC)1162032659 \|z (OCoLC)1192348045 \|z (OCoLC)1227634132 \|z (OCoLC)1228619455 \|z (OCoLC)1434172865
037			\|a 115956:116054 \|b Elsevier Science & Technology \|n http://www.sciencedirect.com
050		4	\|a TK7895.G36 \|b W55 2007eb
072		7	\|a TEC \|x 008050 \|2 bisacsh
072		7	\|a TEC \|x 008030 \|2 bisacsh
072		7	\|a COM \|x 036000 \|2 bisacsh
082	7		\|a 621.395 \|2 22
049			\|a MAIN
100	1		\|a Wilson, Peter R. \|q (Peter Robert), \|d 1939- \|1 https://id.oclc.org/worldcat/entity/E39PCjFMKDdCWt8T3vcQdCfrMP \|0 http://id.loc.gov/authorities/names/nb2001079508
245	1	0	\|a Design recipes for FPGAs / \|c Peter R. Wilson.
260			\|a Amsterdam ; \|a Boston ; \|a London : \|b Newnes, \|c 2007.
300			\|a 1 online resource (xxii, 289 pages :)
336			\|a text \|b txt \|2 rdacontent
337			\|a computer \|b c \|2 rdamedia
338			\|a online resource \|b cr \|2 rdacarrier
504			\|a Includes bibliographical references (pages 284-285) and index.
588	0		\|a Print version record.
505	0		\|a Front cover; Design Recipes for FPGAs; Copyright page; Contents; Acknowledgements; Preface; List of Figures; Part 1 Overview; Part 2 Applications; Part 3 Designer's Toolbox; Part 4 Optimizing Designs; Part 5 Fundamental Techniques; Index.
520			\|a A rich treasure chest of design techniques and templates for solving practical, every-day problems using FPGAs.
650		0	\|a Field programmable gate arrays \|x Design and construction.
650		0	\|a Gate array circuits. \|0 http://id.loc.gov/authorities/subjects/sh86007843
650		6	\|a Circuits prédiffusés.
650		7	\|a TECHNOLOGY & ENGINEERING \|x Electronics \|x Circuits \|x VLSI & ULSI. \|2 bisacsh
650		7	\|a TECHNOLOGY & ENGINEERING \|x Electronics \|x Circuits \|x Logic. \|2 bisacsh
650		7	\|a COMPUTERS \|x Logic Design. \|2 bisacsh
650		7	\|a Field programmable gate arrays \|x Design and construction \|2 fast
655		7	\|a dissertations. \|2 aat
655		7	\|a Academic theses \|2 fast
655		7	\|a Academic theses. \|2 lcgft \|0 http://id.loc.gov/authorities/genreForms/gf2014026039
655		7	\|a Thèses et écrits académiques. \|2 rvmgf
758			\|i has work: \|a Design Recipes for FPGAs: Using Verilog and VHDL. 2nd edition (Text) \|1 https://id.oclc.org/worldcat/entity/E39PD3j3V7R8TJCdtgh897k8P3 \|4 https://id.oclc.org/worldcat/ontology/hasWork
776	0	8	\|i Print version: \|a Wilson, Peter R. (Peter Robert), 1939- \|t Design recipes for FPGAs. \|d Amsterdam ; Boston ; London : Newnes, 2007 \|z 9780750668453 \|z 0750668458 \|w (OCoLC)85829383
856	1		\|l FWS01 \|p ZDB-4-EBA \|q FWS_PDA_EBA \|u https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=203412 \|3 Volltext
856	1		\|l CBO01 \|p ZDB-4-EBA \|q FWS_PDA_EBA \|u https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=203412 \|3 Volltext
856	1		\|l FWS01 \|p ZDB-4-EBA \|q FWS_PDA_EBA \|u https://www.sciencedirect.com/science/book/9780750668453 \|3 Volltext
856	1		\|l CBO01 \|p ZDB-4-EBA \|q FWS_PDA_EBA \|u https://www.sciencedirect.com/science/book/9780750668453 \|3 Volltext
938			\|a Baker & Taylor \|b BKTY \|c 49.95 \|d 49.95 \|i 0750668458 \|n 0007155095 \|s active
938			\|a ebrary \|b EBRY \|n ebr10188606
938			\|a EBSCOhost \|b EBSC \|n 203412
938			\|a YBP Library Services \|b YANK \|n 2614826
994			\|a 92 \|b GEBAY
912			\|a ZDB-4-EBA

Datensatz im Suchindex

DE-BY-FWS_katkey	ZDB-4-EBA-ocn173502373
_version_	1813903305434202112
adam_text
any_adam_object
author	Wilson, Peter R. (Peter Robert), 1939-
author_GND	http://id.loc.gov/authorities/names/nb2001079508
author_facet	Wilson, Peter R. (Peter Robert), 1939-
author_role
author_sort	Wilson, Peter R. 1939-
author_variant	p r w pr prw
building	Verbundindex
bvnumber	localFWS
callnumber-first	T - Technology
callnumber-label	TK7895
callnumber-raw	TK7895.G36 W55 2007eb
callnumber-search	TK7895.G36 W55 2007eb
callnumber-sort	TK 47895 G36 W55 42007EB
callnumber-subject	TK - Electrical and Nuclear Engineering
collection	ZDB-4-EBA
contents	Front cover; Design Recipes for FPGAs; Copyright page; Contents; Acknowledgements; Preface; List of Figures; Part 1 Overview; Part 2 Applications; Part 3 Designer's Toolbox; Part 4 Optimizing Designs; Part 5 Fundamental Techniques; Index.
ctrlnum	(OCoLC)173502373
dewey-full	621.395
dewey-hundreds	600 - Technology (Applied sciences)
dewey-ones	621 - Applied physics
dewey-raw	621.395
dewey-search	621.395
dewey-sort	3621.395
dewey-tens	620 - Engineering and allied operations
discipline	Elektrotechnik / Elektronik / Nachrichtentechnik
format	Electronic eBook
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>04356cam a2200637 a 4500</leader><controlfield tag="001">ZDB-4-EBA-ocn173502373</controlfield><controlfield tag="003">OCoLC</controlfield><controlfield tag="005">20240705115654.0</controlfield><controlfield tag="006">m o d </controlfield><controlfield tag="007">cr cnu---unuuu</controlfield><controlfield tag="008">070929s2007 ne a ob 001 0 eng d</controlfield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">N$T</subfield><subfield code="b">eng</subfield><subfield code="e">pn</subfield><subfield code="c">N$T</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">YDXCP</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">IDEBK</subfield><subfield code="d">E7B</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">MERUC</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">OCLCF</subfield><subfield code="d">ZI0</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">OPELS</subfield><subfield code="d">BAKER</subfield><subfield code="d">UMI</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">COO</subfield><subfield code="d">LOA</subfield><subfield code="d">DEBBG</subfield><subfield code="d">COCUF</subfield><subfield code="d">AGLDB</subfield><subfield code="d">STF</subfield><subfield code="d">MOR</subfield><subfield code="d">PIFAG</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">JBG</subfield><subfield code="d">U3W</subfield><subfield code="d">WRM</subfield><subfield code="d">D6H</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">VTS</subfield><subfield code="d">CEF</subfield><subfield code="d">INT</subfield><subfield code="d">VT2</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">LEAUB</subfield><subfield code="d">M8D</subfield><subfield code="d">HS0</subfield><subfield code="d">UWK</subfield><subfield code="d">UKBTH</subfield><subfield code="d">UKCRE</subfield><subfield code="d">UKSSU</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">OCLCO</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">KSU</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">OCLCO</subfield><subfield code="d">OCLCL</subfield><subfield code="d">EZC</subfield><subfield code="d">QGK</subfield><subfield code="d">OCLCO</subfield></datafield><datafield tag="019" ind1=" " ind2=" "><subfield code="a">162591610</subfield><subfield code="a">648316386</subfield><subfield code="a">811269691</subfield><subfield code="a">931874288</subfield><subfield code="a">961695269</subfield><subfield code="a">962729704</subfield><subfield code="a">966200456</subfield><subfield code="a">984784290</subfield><subfield code="a">988441831</subfield><subfield code="a">992027249</subfield><subfield code="a">1034916821</subfield><subfield code="a">1037739629</subfield><subfield code="a">1038605848</subfield><subfield code="a">1055348826</subfield><subfield code="a">1081216825</subfield><subfield code="a">1109116352</subfield><subfield code="a">1110363412</subfield><subfield code="a">1113567517</subfield><subfield code="a">1152993080</subfield><subfield code="a">1154865067</subfield><subfield code="a">1159645743</subfield><subfield code="a">1162032659</subfield><subfield code="a">1192348045</subfield><subfield code="a">1227634132</subfield><subfield code="a">1228619455</subfield><subfield code="a">1434172865</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780080548425</subfield><subfield code="q">(electronic bk.)</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0080548423</subfield><subfield code="q">(electronic bk.)</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="z">9780750668453</subfield><subfield code="q">(pbk.)</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="z">0750668458</subfield><subfield code="q">(pbk.)</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)173502373</subfield><subfield code="z">(OCoLC)162591610</subfield><subfield code="z">(OCoLC)648316386</subfield><subfield code="z">(OCoLC)811269691</subfield><subfield code="z">(OCoLC)931874288</subfield><subfield code="z">(OCoLC)961695269</subfield><subfield code="z">(OCoLC)962729704</subfield><subfield code="z">(OCoLC)966200456</subfield><subfield code="z">(OCoLC)984784290</subfield><subfield code="z">(OCoLC)988441831</subfield><subfield code="z">(OCoLC)992027249</subfield><subfield code="z">(OCoLC)1034916821</subfield><subfield code="z">(OCoLC)1037739629</subfield><subfield code="z">(OCoLC)1038605848</subfield><subfield code="z">(OCoLC)1055348826</subfield><subfield code="z">(OCoLC)1081216825</subfield><subfield code="z">(OCoLC)1109116352</subfield><subfield code="z">(OCoLC)1110363412</subfield><subfield code="z">(OCoLC)1113567517</subfield><subfield code="z">(OCoLC)1152993080</subfield><subfield code="z">(OCoLC)1154865067</subfield><subfield code="z">(OCoLC)1159645743</subfield><subfield code="z">(OCoLC)1162032659</subfield><subfield code="z">(OCoLC)1192348045</subfield><subfield code="z">(OCoLC)1227634132</subfield><subfield code="z">(OCoLC)1228619455</subfield><subfield code="z">(OCoLC)1434172865</subfield></datafield><datafield tag="037" ind1=" " ind2=" "><subfield code="a">115956:116054</subfield><subfield code="b">Elsevier Science & Technology</subfield><subfield code="n">http://www.sciencedirect.com</subfield></datafield><datafield tag="050" ind1=" " ind2="4"><subfield code="a">TK7895.G36</subfield><subfield code="b">W55 2007eb</subfield></datafield><datafield tag="072" ind1=" " ind2="7"><subfield code="a">TEC</subfield><subfield code="x">008050</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="072" ind1=" " ind2="7"><subfield code="a">TEC</subfield><subfield code="x">008030</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="072" ind1=" " ind2="7"><subfield code="a">COM</subfield><subfield code="x">036000</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="082" ind1="7" ind2=" "><subfield code="a">621.395</subfield><subfield code="2">22</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">MAIN</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Wilson, Peter R.</subfield><subfield code="q">(Peter Robert),</subfield><subfield code="d">1939-</subfield><subfield code="1">https://id.oclc.org/worldcat/entity/E39PCjFMKDdCWt8T3vcQdCfrMP</subfield><subfield code="0">http://id.loc.gov/authorities/names/nb2001079508</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Design recipes for FPGAs /</subfield><subfield code="c">Peter R. Wilson.</subfield></datafield><datafield tag="260" ind1=" " ind2=" "><subfield code="a">Amsterdam ;</subfield><subfield code="a">Boston ;</subfield><subfield code="a">London :</subfield><subfield code="b">Newnes,</subfield><subfield code="c">2007.</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 online resource (xxii, 289 pages :)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">computer</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">online resource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="504" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references (pages 284-285) and index.</subfield></datafield><datafield tag="588" ind1="0" ind2=" "><subfield code="a">Print version record.</subfield></datafield><datafield tag="505" ind1="0" ind2=" "><subfield code="a">Front cover; Design Recipes for FPGAs; Copyright page; Contents; Acknowledgements; Preface; List of Figures; Part 1 Overview; Part 2 Applications; Part 3 Designer's Toolbox; Part 4 Optimizing Designs; Part 5 Fundamental Techniques; Index.</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">A rich treasure chest of design techniques and templates for solving practical, every-day problems using FPGAs.</subfield></datafield><datafield tag="650" ind1=" " ind2="0"><subfield code="a">Field programmable gate arrays</subfield><subfield code="x">Design and construction.</subfield></datafield><datafield tag="650" ind1=" " ind2="0"><subfield code="a">Gate array circuits.</subfield><subfield code="0">http://id.loc.gov/authorities/subjects/sh86007843</subfield></datafield><datafield tag="650" ind1=" " ind2="6"><subfield code="a">Circuits prédiffusés.</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING</subfield><subfield code="x">Electronics</subfield><subfield code="x">Circuits</subfield><subfield code="x">VLSI & ULSI.</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING</subfield><subfield code="x">Electronics</subfield><subfield code="x">Circuits</subfield><subfield code="x">Logic.</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">COMPUTERS</subfield><subfield code="x">Logic Design.</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Field programmable gate arrays</subfield><subfield code="x">Design and construction</subfield><subfield code="2">fast</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="a">dissertations.</subfield><subfield code="2">aat</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="a">Academic theses</subfield><subfield code="2">fast</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="a">Academic theses.</subfield><subfield code="2">lcgft</subfield><subfield code="0">http://id.loc.gov/authorities/genreForms/gf2014026039</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="a">Thèses et écrits académiques.</subfield><subfield code="2">rvmgf</subfield></datafield><datafield tag="758" ind1=" " ind2=" "><subfield code="i">has work:</subfield><subfield code="a">Design Recipes for FPGAs: Using Verilog and VHDL. 2nd edition (Text)</subfield><subfield code="1">https://id.oclc.org/worldcat/entity/E39PD3j3V7R8TJCdtgh897k8P3</subfield><subfield code="4">https://id.oclc.org/worldcat/ontology/hasWork</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Print version:</subfield><subfield code="a">Wilson, Peter R. (Peter Robert), 1939-</subfield><subfield code="t">Design recipes for FPGAs.</subfield><subfield code="d">Amsterdam ; Boston ; London : Newnes, 2007</subfield><subfield code="z">9780750668453</subfield><subfield code="z">0750668458</subfield><subfield code="w">(OCoLC)85829383</subfield></datafield><datafield tag="856" ind1="1" ind2=" "><subfield code="l">FWS01</subfield><subfield code="p">ZDB-4-EBA</subfield><subfield code="q">FWS_PDA_EBA</subfield><subfield code="u">https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=203412</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="1" ind2=" "><subfield code="l">CBO01</subfield><subfield code="p">ZDB-4-EBA</subfield><subfield code="q">FWS_PDA_EBA</subfield><subfield code="u">https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=203412</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="1" ind2=" "><subfield code="l">FWS01</subfield><subfield code="p">ZDB-4-EBA</subfield><subfield code="q">FWS_PDA_EBA</subfield><subfield code="u">https://www.sciencedirect.com/science/book/9780750668453</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="1" ind2=" "><subfield code="l">CBO01</subfield><subfield code="p">ZDB-4-EBA</subfield><subfield code="q">FWS_PDA_EBA</subfield><subfield code="u">https://www.sciencedirect.com/science/book/9780750668453</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="938" ind1=" " ind2=" "><subfield code="a">Baker & Taylor</subfield><subfield code="b">BKTY</subfield><subfield code="c">49.95</subfield><subfield code="d">49.95</subfield><subfield code="i">0750668458</subfield><subfield code="n">0007155095</subfield><subfield code="s">active</subfield></datafield><datafield tag="938" ind1=" " ind2=" "><subfield code="a">ebrary</subfield><subfield code="b">EBRY</subfield><subfield code="n">ebr10188606</subfield></datafield><datafield tag="938" ind1=" " ind2=" "><subfield code="a">EBSCOhost</subfield><subfield code="b">EBSC</subfield><subfield code="n">203412</subfield></datafield><datafield tag="938" ind1=" " ind2=" "><subfield code="a">YBP Library Services</subfield><subfield code="b">YANK</subfield><subfield code="n">2614826</subfield></datafield><datafield tag="994" ind1=" " ind2=" "><subfield code="a">92</subfield><subfield code="b">GEBAY</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-4-EBA</subfield></datafield></record></collection>
genre	dissertations. aat Academic theses fast Academic theses. lcgft http://id.loc.gov/authorities/genreForms/gf2014026039 Thèses et écrits académiques. rvmgf
genre_facet	dissertations. Academic theses Academic theses. Thèses et écrits académiques.
id	ZDB-4-EBA-ocn173502373
illustrated	Illustrated
indexdate	2024-10-25T16:16:34Z
institution	BVB
isbn	9780080548425 0080548423
language	English
oclc_num	173502373
open_access_boolean
owner	MAIN
owner_facet	MAIN
physical	1 online resource (xxii, 289 pages :)
psigel	ZDB-4-EBA
publishDate	2007
publishDateSearch	2007
publishDateSort	2007
publisher	Newnes,
record_format	marc
spelling	Wilson, Peter R. (Peter Robert), 1939- https://id.oclc.org/worldcat/entity/E39PCjFMKDdCWt8T3vcQdCfrMP http://id.loc.gov/authorities/names/nb2001079508 Design recipes for FPGAs / Peter R. Wilson. Amsterdam ; Boston ; London : Newnes, 2007. 1 online resource (xxii, 289 pages :) text txt rdacontent computer c rdamedia online resource cr rdacarrier Includes bibliographical references (pages 284-285) and index. Print version record. Front cover; Design Recipes for FPGAs; Copyright page; Contents; Acknowledgements; Preface; List of Figures; Part 1 Overview; Part 2 Applications; Part 3 Designer's Toolbox; Part 4 Optimizing Designs; Part 5 Fundamental Techniques; Index. A rich treasure chest of design techniques and templates for solving practical, every-day problems using FPGAs. Field programmable gate arrays Design and construction. Gate array circuits. http://id.loc.gov/authorities/subjects/sh86007843 Circuits prédiffusés. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits Logic. bisacsh COMPUTERS Logic Design. bisacsh Field programmable gate arrays Design and construction fast dissertations. aat Academic theses fast Academic theses. lcgft http://id.loc.gov/authorities/genreForms/gf2014026039 Thèses et écrits académiques. rvmgf has work: Design Recipes for FPGAs: Using Verilog and VHDL. 2nd edition (Text) https://id.oclc.org/worldcat/entity/E39PD3j3V7R8TJCdtgh897k8P3 https://id.oclc.org/worldcat/ontology/hasWork Print version: Wilson, Peter R. (Peter Robert), 1939- Design recipes for FPGAs. Amsterdam ; Boston ; London : Newnes, 2007 9780750668453 0750668458 (OCoLC)85829383 FWS01 ZDB-4-EBA FWS_PDA_EBA https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=203412 Volltext CBO01 ZDB-4-EBA FWS_PDA_EBA https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=203412 Volltext FWS01 ZDB-4-EBA FWS_PDA_EBA https://www.sciencedirect.com/science/book/9780750668453 Volltext CBO01 ZDB-4-EBA FWS_PDA_EBA https://www.sciencedirect.com/science/book/9780750668453 Volltext
spellingShingle	Wilson, Peter R. (Peter Robert), 1939- Design recipes for FPGAs / Front cover; Design Recipes for FPGAs; Copyright page; Contents; Acknowledgements; Preface; List of Figures; Part 1 Overview; Part 2 Applications; Part 3 Designer's Toolbox; Part 4 Optimizing Designs; Part 5 Fundamental Techniques; Index. Field programmable gate arrays Design and construction. Gate array circuits. http://id.loc.gov/authorities/subjects/sh86007843 Circuits prédiffusés. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits Logic. bisacsh COMPUTERS Logic Design. bisacsh Field programmable gate arrays Design and construction fast
subject_GND	http://id.loc.gov/authorities/subjects/sh86007843 http://id.loc.gov/authorities/genreForms/gf2014026039
title	Design recipes for FPGAs /
title_auth	Design recipes for FPGAs /
title_exact_search	Design recipes for FPGAs /
title_full	Design recipes for FPGAs / Peter R. Wilson.
title_fullStr	Design recipes for FPGAs / Peter R. Wilson.
title_full_unstemmed	Design recipes for FPGAs / Peter R. Wilson.
title_short	Design recipes for FPGAs /
title_sort	design recipes for fpgas
topic	Field programmable gate arrays Design and construction. Gate array circuits. http://id.loc.gov/authorities/subjects/sh86007843 Circuits prédiffusés. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits Logic. bisacsh COMPUTERS Logic Design. bisacsh Field programmable gate arrays Design and construction fast
topic_facet	Field programmable gate arrays Design and construction. Gate array circuits. Circuits prédiffusés. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. TECHNOLOGY & ENGINEERING Electronics Circuits Logic. COMPUTERS Logic Design. Field programmable gate arrays Design and construction dissertations. Academic theses Academic theses. Thèses et écrits académiques.
url	https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=203412 https://www.sciencedirect.com/science/book/9780750668453
work_keys_str_mv	AT wilsonpeterr designrecipesforfpgas

Verfügbarkeit

Es ist kein Print-Exemplar vorhanden.

Fernleihe Bestellen Achtung: Nicht im THWS-Bestand! Volltext öffnen

MARC

Datensatz im Suchindex

Es ist kein Print-Exemplar vorhanden.

Ähnliche Einträge