VLSI test principles and architectures :: design for testability /
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of indu...
Gespeichert in:
| Weitere Verfasser: | , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam ; Boston :
Elsevier Morgan Kaufmann Publishers,
[2006]
|
| Schriftenreihe: | Morgan Kaufmann series in systems on silicon.
|
| Schlagworte: | |
| Online-Zugang: | DE-862 DE-863 DE-862 DE-863 |
| Zusammenfassung: | This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website. |
| Beschreibung: | 1 online resource (xxx, 777 pages) : illustrations |
| Bibliographie: | Includes bibliographical references and index. |
| ISBN: | 9780080474793 0080474799 |
Internformat
MARC
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| 245 | 0 | 0 | |a VLSI test principles and architectures : |b design for testability / |c edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen. |
| 264 | 1 | |a Amsterdam ; |a Boston : |b Elsevier Morgan Kaufmann Publishers, |c [2006] | |
| 264 | 4 | |c ©2006 | |
| 300 | |a 1 online resource (xxx, 777 pages) : |b illustrations | ||
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| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a The Morgan Kaufmann series in systems on silicon | |
| 504 | |a Includes bibliographical references and index. | ||
| 505 | 0 | |a Design for testability / Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez -- Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker -- Test generation / Michael S. Hsiao -- Logic built-in self-test / Laung-Terng (L.-T.) Wang -- Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba -- Logic diagnosis / Shi-Yu Huang -- Memory testing and built-in self-test / Cheng-Wen Wu -- Memory diagnosis and built-in self-repair / Cheng-Wen Wu -- Boundary scan and core-based testing / Kuen-Jong Lee -- Analog and mixed-signal testing / Chauchin Su -- Test technology trends in the nanometer age / Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang. | |
| 520 | |a This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website. | ||
| 588 | 0 | |a Print version record. | |
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Testing. | |
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Design. | |
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Design and construction. | |
| 650 | 6 | |a Circuits intégrés à très grande échelle |x Essais. | |
| 650 | 6 | |a Circuits intégrés à très grande échelle |x Conception et construction. | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x VLSI & ULSI. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x Logic. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Logic Design. |2 bisacsh | |
| 650 | 7 | |a Integrated circuits |x Very large scale integration |x Testing. |2 blmlsh | |
| 650 | 7 | |a Integrated circuits |x Very large scale integration |x Design. |2 blmlsh | |
| 650 | 7 | |a Integrated circuits |x Very large scale integration |x Design and construction |2 fast | |
| 650 | 7 | |a Integrated circuits |x Very large scale integration |x Design |2 fast | |
| 650 | 7 | |a Integrated circuits |x Very large scale integration |x Testing |2 fast | |
| 650 | 7 | |a Testen |2 gnd | |
| 650 | 7 | |a VLSI |2 gnd |0 http://d-nb.info/gnd/4117388-0 | |
| 650 | 7 | |a Circuitos integrados vlsi. |2 larpcal | |
| 655 | 7 | |a dissertations. |2 aat | |
| 655 | 7 | |a Academic theses |2 fast | |
| 655 | 7 | |a Academic theses. |2 lcgft |0 http://id.loc.gov/authorities/genreForms/gf2014026039 | |
| 655 | 7 | |a Thèses et écrits académiques. |2 rvmgf | |
| 700 | 1 | |a Wang, Laung-Terng, |e editor. | |
| 700 | 1 | |a Wu, Cheng-Wen, |c EE Ph. D., |e editor. |1 https://id.oclc.org/worldcat/entity/E39PCjxmfVgHb6DmrxWJWjR4tq |0 http://id.loc.gov/authorities/names/n2006014252 | |
| 700 | 1 | |a Wen, Xiaoqing, |e editor. | |
| 758 | |i has work: |a VLSI test principles and architectures (Text) |1 https://id.oclc.org/worldcat/entity/E39PCFxhv3HCbPPD6VKyC8VWfy |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
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Datensatz im Suchindex
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| author2 | Wang, Laung-Terng Wu, Cheng-Wen, EE Ph. D. Wen, Xiaoqing |
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| contents | Design for testability / Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez -- Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker -- Test generation / Michael S. Hsiao -- Logic built-in self-test / Laung-Terng (L.-T.) Wang -- Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba -- Logic diagnosis / Shi-Yu Huang -- Memory testing and built-in self-test / Cheng-Wen Wu -- Memory diagnosis and built-in self-repair / Cheng-Wen Wu -- Boundary scan and core-based testing / Kuen-Jong Lee -- Analog and mixed-signal testing / Chauchin Su -- Test technology trends in the nanometer age / Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang. |
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| genre | dissertations. aat Academic theses fast Academic theses. lcgft http://id.loc.gov/authorities/genreForms/gf2014026039 Thèses et écrits académiques. rvmgf |
| genre_facet | dissertations. Academic theses Academic theses. Thèses et écrits académiques. |
| id | ZDB-4-EBA-ocn162573568 |
| illustrated | Illustrated |
| indexdate | 2025-04-11T08:35:53Z |
| institution | BVB |
| isbn | 9780080474793 0080474799 |
| language | English |
| lccn | 2006006869 |
| oclc_num | 162573568 |
| open_access_boolean | |
| owner | MAIN DE-862 DE-BY-FWS DE-863 DE-BY-FWS |
| owner_facet | MAIN DE-862 DE-BY-FWS DE-863 DE-BY-FWS |
| physical | 1 online resource (xxx, 777 pages) : illustrations |
| psigel | ZDB-4-EBA FWS_PDA_EBA ZDB-4-EBA |
| publishDate | 2006 |
| publishDateSearch | 2006 |
| publishDateSort | 2006 |
| publisher | Elsevier Morgan Kaufmann Publishers, |
| record_format | marc |
| series | Morgan Kaufmann series in systems on silicon. |
| series2 | The Morgan Kaufmann series in systems on silicon |
| spelling | VLSI test principles and architectures : design for testability / edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen. Amsterdam ; Boston : Elsevier Morgan Kaufmann Publishers, [2006] ©2006 1 online resource (xxx, 777 pages) : illustrations text txt rdacontent computer c rdamedia online resource cr rdacarrier The Morgan Kaufmann series in systems on silicon Includes bibliographical references and index. Design for testability / Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez -- Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker -- Test generation / Michael S. Hsiao -- Logic built-in self-test / Laung-Terng (L.-T.) Wang -- Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba -- Logic diagnosis / Shi-Yu Huang -- Memory testing and built-in self-test / Cheng-Wen Wu -- Memory diagnosis and built-in self-repair / Cheng-Wen Wu -- Boundary scan and core-based testing / Kuen-Jong Lee -- Analog and mixed-signal testing / Chauchin Su -- Test technology trends in the nanometer age / Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang. This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website. Print version record. Integrated circuits Very large scale integration Testing. Integrated circuits Very large scale integration Design. Integrated circuits Very large scale integration Design and construction. Circuits intégrés à très grande échelle Essais. Circuits intégrés à très grande échelle Conception et construction. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits Logic. bisacsh COMPUTERS Logic Design. bisacsh Integrated circuits Very large scale integration Testing. blmlsh Integrated circuits Very large scale integration Design. blmlsh Integrated circuits Very large scale integration Design and construction fast Integrated circuits Very large scale integration Design fast Integrated circuits Very large scale integration Testing fast Testen gnd VLSI gnd http://d-nb.info/gnd/4117388-0 Circuitos integrados vlsi. larpcal dissertations. aat Academic theses fast Academic theses. lcgft http://id.loc.gov/authorities/genreForms/gf2014026039 Thèses et écrits académiques. rvmgf Wang, Laung-Terng, editor. Wu, Cheng-Wen, EE Ph. D., editor. https://id.oclc.org/worldcat/entity/E39PCjxmfVgHb6DmrxWJWjR4tq http://id.loc.gov/authorities/names/n2006014252 Wen, Xiaoqing, editor. has work: VLSI test principles and architectures (Text) https://id.oclc.org/worldcat/entity/E39PCFxhv3HCbPPD6VKyC8VWfy https://id.oclc.org/worldcat/ontology/hasWork Print version: VLSI test principles and architectures. Amsterdam ; Boston : Elsevier Morgan Kaufmann Publishers, ©2006 0123705975 9780123705976 (DLC) 2006006869 (OCoLC)64624834 Morgan Kaufmann series in systems on silicon. http://id.loc.gov/authorities/names/n2001146727 |
| spellingShingle | VLSI test principles and architectures : design for testability / Morgan Kaufmann series in systems on silicon. Design for testability / Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez -- Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker -- Test generation / Michael S. Hsiao -- Logic built-in self-test / Laung-Terng (L.-T.) Wang -- Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba -- Logic diagnosis / Shi-Yu Huang -- Memory testing and built-in self-test / Cheng-Wen Wu -- Memory diagnosis and built-in self-repair / Cheng-Wen Wu -- Boundary scan and core-based testing / Kuen-Jong Lee -- Analog and mixed-signal testing / Chauchin Su -- Test technology trends in the nanometer age / Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang. Integrated circuits Very large scale integration Testing. Integrated circuits Very large scale integration Design. Integrated circuits Very large scale integration Design and construction. Circuits intégrés à très grande échelle Essais. Circuits intégrés à très grande échelle Conception et construction. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits Logic. bisacsh COMPUTERS Logic Design. bisacsh Integrated circuits Very large scale integration Testing. blmlsh Integrated circuits Very large scale integration Design. blmlsh Integrated circuits Very large scale integration Design and construction fast Integrated circuits Very large scale integration Design fast Integrated circuits Very large scale integration Testing fast Testen gnd VLSI gnd http://d-nb.info/gnd/4117388-0 Circuitos integrados vlsi. larpcal |
| subject_GND | http://d-nb.info/gnd/4117388-0 http://id.loc.gov/authorities/genreForms/gf2014026039 |
| title | VLSI test principles and architectures : design for testability / |
| title_auth | VLSI test principles and architectures : design for testability / |
| title_exact_search | VLSI test principles and architectures : design for testability / |
| title_full | VLSI test principles and architectures : design for testability / edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen. |
| title_fullStr | VLSI test principles and architectures : design for testability / edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen. |
| title_full_unstemmed | VLSI test principles and architectures : design for testability / edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen. |
| title_short | VLSI test principles and architectures : |
| title_sort | vlsi test principles and architectures design for testability |
| title_sub | design for testability / |
| topic | Integrated circuits Very large scale integration Testing. Integrated circuits Very large scale integration Design. Integrated circuits Very large scale integration Design and construction. Circuits intégrés à très grande échelle Essais. Circuits intégrés à très grande échelle Conception et construction. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits Logic. bisacsh COMPUTERS Logic Design. bisacsh Integrated circuits Very large scale integration Testing. blmlsh Integrated circuits Very large scale integration Design. blmlsh Integrated circuits Very large scale integration Design and construction fast Integrated circuits Very large scale integration Design fast Integrated circuits Very large scale integration Testing fast Testen gnd VLSI gnd http://d-nb.info/gnd/4117388-0 Circuitos integrados vlsi. larpcal |
| topic_facet | Integrated circuits Very large scale integration Testing. Integrated circuits Very large scale integration Design. Integrated circuits Very large scale integration Design and construction. Circuits intégrés à très grande échelle Essais. Circuits intégrés à très grande échelle Conception et construction. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. TECHNOLOGY & ENGINEERING Electronics Circuits Logic. COMPUTERS Logic Design. Integrated circuits Very large scale integration Design and construction Integrated circuits Very large scale integration Design Integrated circuits Very large scale integration Testing Testen VLSI Circuitos integrados vlsi. dissertations. Academic theses Academic theses. Thèses et écrits académiques. |
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