VHDL :: coding and logic synthesis with Synopsys /
This book provides the most up-to-date coverage using the Synopsys program in the design of integrated circuits. The incorporation of "synthesis tools" is the most popular new method of designing integrated circuits for higher speeds covering smaller surface areas. Synopsys is the dominant...
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
San Diego :
Academic Press,
©2000.
|
| Schlagworte: | |
| Online-Zugang: | Volltext Volltext |
| Zusammenfassung: | This book provides the most up-to-date coverage using the Synopsys program in the design of integrated circuits. The incorporation of "synthesis tools" is the most popular new method of designing integrated circuits for higher speeds covering smaller surface areas. Synopsys is the dominant computer-aided circuit design program in the world. All of the major circuit manufacturers and ASIC design firms use Synopsys. In addition, Synopsys is used in teaching and laboratories at over 600 universities. * First practical guide to using synthesis with Synopsys * Synopsys is the #1 design program for IC design |
| Beschreibung: | 1 online resource (xxiv, 392 pages) |
| Bibliographie: | Includes bibliographical references and index. |
| ISBN: | 9780124406513 0124406513 9780080520506 0080520502 1281046701 9781281046703 |
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| 505 | 0 | |a List of Figures. -- List of Tables. -- List of Examples. -- Preface. -- Acknowledgement. -- Trademarks. -- I. VHDL CODING -- 1. Introduction. -- 2. VHDL Simulation and Synthesis Flow. -- 3. Synthesizable Code for Basic Logic Components. -- 4. Signal Versus Variable. -- 5. Examples of Complex Synthesizable Code. -- 6. Pipeline Microcontroller Synthesizable Design. -- II. LOGIC SYNTHESIS WITH SYNOPSYS. -- 7. Timing Considerations in Design. -- 8. VHDL Synthesis with Timing Constraints. -- 9. GTECH Instantiation. -- 10. DesignWare Library. -- 11. Testability Issues in Synthesis. -- 12. FPGA Synthesis. -- 13. Synthesis Links to Layout. -- 14. Design Guideline to Follow for Efficient Synthesis. -- 15. Appendix A (STD_LOGIC_1164 Library). -- 16. Appendix B (Shifter Synthesis Results). -- 17. Appendix C (Counter Synthesis Results). -- 18. Appendix D (Pipeline Microcontroller Synthesis Results--Top-Down Compilation). -- 19. Appendix E (EDIF File of Synthesized Microcontroller Example from Chapter 6). -- 20. Appendix F (SDF File from Synthesized Microcontroller Example of Chapter 6). -- Glossary. -- Bibliography. -- Index. | |
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| contents | List of Figures. -- List of Tables. -- List of Examples. -- Preface. -- Acknowledgement. -- Trademarks. -- I. VHDL CODING -- 1. Introduction. -- 2. VHDL Simulation and Synthesis Flow. -- 3. Synthesizable Code for Basic Logic Components. -- 4. Signal Versus Variable. -- 5. Examples of Complex Synthesizable Code. -- 6. Pipeline Microcontroller Synthesizable Design. -- II. LOGIC SYNTHESIS WITH SYNOPSYS. -- 7. Timing Considerations in Design. -- 8. VHDL Synthesis with Timing Constraints. -- 9. GTECH Instantiation. -- 10. DesignWare Library. -- 11. Testability Issues in Synthesis. -- 12. FPGA Synthesis. -- 13. Synthesis Links to Layout. -- 14. Design Guideline to Follow for Efficient Synthesis. -- 15. Appendix A (STD_LOGIC_1164 Library). -- 16. Appendix B (Shifter Synthesis Results). -- 17. Appendix C (Counter Synthesis Results). -- 18. Appendix D (Pipeline Microcontroller Synthesis Results--Top-Down Compilation). -- 19. Appendix E (EDIF File of Synthesized Microcontroller Example from Chapter 6). -- 20. Appendix F (SDF File from Synthesized Microcontroller Example of Chapter 6). -- Glossary. -- Bibliography. -- Index. |
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| illustrated | Not Illustrated |
| indexdate | 2024-11-27T13:16:05Z |
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| language | English |
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| spelling | Lee, Weng Fook. https://id.oclc.org/worldcat/entity/E39PCjrVy4gTwHghmwFKQvBrjd http://id.loc.gov/authorities/names/no00096782 VHDL : coding and logic synthesis with Synopsys / Weng Fook Lee. San Diego : Academic Press, ©2000. 1 online resource (xxiv, 392 pages) text txt rdacontent computer c rdamedia online resource cr rdacarrier This book provides the most up-to-date coverage using the Synopsys program in the design of integrated circuits. The incorporation of "synthesis tools" is the most popular new method of designing integrated circuits for higher speeds covering smaller surface areas. Synopsys is the dominant computer-aided circuit design program in the world. All of the major circuit manufacturers and ASIC design firms use Synopsys. In addition, Synopsys is used in teaching and laboratories at over 600 universities. * First practical guide to using synthesis with Synopsys * Synopsys is the #1 design program for IC design List of Figures. -- List of Tables. -- List of Examples. -- Preface. -- Acknowledgement. -- Trademarks. -- I. VHDL CODING -- 1. Introduction. -- 2. VHDL Simulation and Synthesis Flow. -- 3. Synthesizable Code for Basic Logic Components. -- 4. Signal Versus Variable. -- 5. Examples of Complex Synthesizable Code. -- 6. Pipeline Microcontroller Synthesizable Design. -- II. LOGIC SYNTHESIS WITH SYNOPSYS. -- 7. Timing Considerations in Design. -- 8. VHDL Synthesis with Timing Constraints. -- 9. GTECH Instantiation. -- 10. DesignWare Library. -- 11. Testability Issues in Synthesis. -- 12. FPGA Synthesis. -- 13. Synthesis Links to Layout. -- 14. Design Guideline to Follow for Efficient Synthesis. -- 15. Appendix A (STD_LOGIC_1164 Library). -- 16. Appendix B (Shifter Synthesis Results). -- 17. Appendix C (Counter Synthesis Results). -- 18. Appendix D (Pipeline Microcontroller Synthesis Results--Top-Down Compilation). -- 19. Appendix E (EDIF File of Synthesized Microcontroller Example from Chapter 6). -- 20. Appendix F (SDF File from Synthesized Microcontroller Example of Chapter 6). -- Glossary. -- Bibliography. -- Index. Print version record. Includes bibliographical references and index. VHDL (Computer hardware description language) http://id.loc.gov/authorities/subjects/sh89002702 VHDL (Langage de description de matériel informatique) COMPUTERS Machine Theory. bisacsh COMPUTERS Computer Engineering. bisacsh COMPUTERS Hardware General. bisacsh VHDL (Computer hardware description language) fast has work: VHDL (Text) https://id.oclc.org/worldcat/entity/E39PCGXf4wq774kFgHPW9bxvBK https://id.oclc.org/worldcat/ontology/hasWork Print version: Lee, Weng Fook. VHDL. San Diego : Academic Press, ©2000 0124406513 9780124406513 (DLC) 00103964 (OCoLC)46793019 FWS01 ZDB-4-EBA FWS_PDA_EBA https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=207412 Volltext FWS01 ZDB-4-EBA FWS_PDA_EBA https://www.sciencedirect.com/science/book/9780124406513 Volltext |
| spellingShingle | Lee, Weng Fook VHDL : coding and logic synthesis with Synopsys / List of Figures. -- List of Tables. -- List of Examples. -- Preface. -- Acknowledgement. -- Trademarks. -- I. VHDL CODING -- 1. Introduction. -- 2. VHDL Simulation and Synthesis Flow. -- 3. Synthesizable Code for Basic Logic Components. -- 4. Signal Versus Variable. -- 5. Examples of Complex Synthesizable Code. -- 6. Pipeline Microcontroller Synthesizable Design. -- II. LOGIC SYNTHESIS WITH SYNOPSYS. -- 7. Timing Considerations in Design. -- 8. VHDL Synthesis with Timing Constraints. -- 9. GTECH Instantiation. -- 10. DesignWare Library. -- 11. Testability Issues in Synthesis. -- 12. FPGA Synthesis. -- 13. Synthesis Links to Layout. -- 14. Design Guideline to Follow for Efficient Synthesis. -- 15. Appendix A (STD_LOGIC_1164 Library). -- 16. Appendix B (Shifter Synthesis Results). -- 17. Appendix C (Counter Synthesis Results). -- 18. Appendix D (Pipeline Microcontroller Synthesis Results--Top-Down Compilation). -- 19. Appendix E (EDIF File of Synthesized Microcontroller Example from Chapter 6). -- 20. Appendix F (SDF File from Synthesized Microcontroller Example of Chapter 6). -- Glossary. -- Bibliography. -- Index. VHDL (Computer hardware description language) http://id.loc.gov/authorities/subjects/sh89002702 VHDL (Langage de description de matériel informatique) COMPUTERS Machine Theory. bisacsh COMPUTERS Computer Engineering. bisacsh COMPUTERS Hardware General. bisacsh VHDL (Computer hardware description language) fast |
| subject_GND | http://id.loc.gov/authorities/subjects/sh89002702 |
| title | VHDL : coding and logic synthesis with Synopsys / |
| title_auth | VHDL : coding and logic synthesis with Synopsys / |
| title_exact_search | VHDL : coding and logic synthesis with Synopsys / |
| title_full | VHDL : coding and logic synthesis with Synopsys / Weng Fook Lee. |
| title_fullStr | VHDL : coding and logic synthesis with Synopsys / Weng Fook Lee. |
| title_full_unstemmed | VHDL : coding and logic synthesis with Synopsys / Weng Fook Lee. |
| title_short | VHDL : |
| title_sort | vhdl coding and logic synthesis with synopsys |
| title_sub | coding and logic synthesis with Synopsys / |
| topic | VHDL (Computer hardware description language) http://id.loc.gov/authorities/subjects/sh89002702 VHDL (Langage de description de matériel informatique) COMPUTERS Machine Theory. bisacsh COMPUTERS Computer Engineering. bisacsh COMPUTERS Hardware General. bisacsh VHDL (Computer hardware description language) fast |
| topic_facet | VHDL (Computer hardware description language) VHDL (Langage de description de matériel informatique) COMPUTERS Machine Theory. COMPUTERS Computer Engineering. COMPUTERS Hardware General. |
| url | https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=207412 https://www.sciencedirect.com/science/book/9780124406513 |
| work_keys_str_mv | AT leewengfook vhdlcodingandlogicsynthesiswithsynopsys |