ASIC and FPGA verification :: a guide to component modeling /
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
San Francisco, Calif. :
Morgan Kaufmann,
©2005.
|
| Schriftenreihe: | Morgan Kaufmann series in systems on silicon.
|
| Schlagworte: | |
| Online-Zugang: | Volltext Volltext |
| Zusammenfassung: | Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification |
| Beschreibung: | Includes index. |
| Beschreibung: | 1 online resource (1 volume). |
| ISBN: | 1417549718 9781417549719 9780125105811 0125105819 9780080475929 0080475922 |
Internformat
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| 520 | |a Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification | ||
| 650 | 0 | |a Application-specific integrated circuits. |0 http://id.loc.gov/authorities/subjects/sh89004045 | |
| 650 | 0 | |a Field programmable gate arrays. |0 http://id.loc.gov/authorities/subjects/sh93009062 | |
| 650 | 6 | |a Circuits intégrés à la demande. | |
| 650 | 6 | |a Réseaux logiques programmables par l'utilisateur. | |
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| contents | 1. Introduction to Board-Level Verification; 2. Tour of a simple model; 3. VHDL packages for component models; 4. Introduction to SDF; 5. Anatomy of a VITAL Model; 6. Modeling Delays; 7. VITAL truth tables; 8. Modeling timing constraints; 9. Modeling registered devices; 10. Conditional delays and timing constraints; 11. Negative timing constraints; 12. Timing Files and Backannotation; 13. Adding Timing to Your RTL Code; 14. Modeling Memories; 15. Considerations for Component Modeling; 16. Modeling Component Centric Features; 17. Testbenches for Component Models. |
| ctrlnum | (OCoLC)56837419 |
| dewey-full | 621.395 |
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| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | ZDB-4-EBA-ocm56837419 |
| illustrated | Not Illustrated |
| indexdate | 2024-11-27T13:15:37Z |
| institution | BVB |
| isbn | 1417549718 9781417549719 9780125105811 0125105819 9780080475929 0080475922 |
| language | English |
| oclc_num | 56837419 |
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| spelling | Munden, Richard. ASIC and FPGA verification : a guide to component modeling / Richard Munden. San Francisco, Calif. : Morgan Kaufmann, ©2005. 1 online resource (1 volume). text txt rdacontent computer c rdamedia online resource cr rdacarrier Morgan Kaufmann series in systems on silicon Includes index. Print version record. 1. Introduction to Board-Level Verification; 2. Tour of a simple model; 3. VHDL packages for component models; 4. Introduction to SDF; 5. Anatomy of a VITAL Model; 6. Modeling Delays; 7. VITAL truth tables; 8. Modeling timing constraints; 9. Modeling registered devices; 10. Conditional delays and timing constraints; 11. Negative timing constraints; 12. Timing Files and Backannotation; 13. Adding Timing to Your RTL Code; 14. Modeling Memories; 15. Considerations for Component Modeling; 16. Modeling Component Centric Features; 17. Testbenches for Component Models. Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification Application-specific integrated circuits. http://id.loc.gov/authorities/subjects/sh89004045 Field programmable gate arrays. http://id.loc.gov/authorities/subjects/sh93009062 Circuits intégrés à la demande. Réseaux logiques programmables par l'utilisateur. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits Logic. bisacsh COMPUTERS Logic Design. bisacsh Application specific integrated circuits. cct Field programmable gate arrays fast Application-specific integrated circuits fast has work: ASIC and FPGA verification (Text) https://id.oclc.org/worldcat/entity/E39PCFyKbYkMW3k6JMwJJ6wRDq https://id.oclc.org/worldcat/ontology/hasWork Print version: Munden, Richard. ASIC and FPGA verification. San Francisco, Calif. : Morgan Kaufmann, ©2005 0125105819 (OCoLC)56642597 Morgan Kaufmann series in systems on silicon. http://id.loc.gov/authorities/names/n2001146727 FWS01 ZDB-4-EBA FWS_PDA_EBA https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=117163 Volltext FWS01 ZDB-4-EBA FWS_PDA_EBA https://www.sciencedirect.com/science/book/9780125105811 Volltext |
| spellingShingle | Munden, Richard ASIC and FPGA verification : a guide to component modeling / Morgan Kaufmann series in systems on silicon. 1. Introduction to Board-Level Verification; 2. Tour of a simple model; 3. VHDL packages for component models; 4. Introduction to SDF; 5. Anatomy of a VITAL Model; 6. Modeling Delays; 7. VITAL truth tables; 8. Modeling timing constraints; 9. Modeling registered devices; 10. Conditional delays and timing constraints; 11. Negative timing constraints; 12. Timing Files and Backannotation; 13. Adding Timing to Your RTL Code; 14. Modeling Memories; 15. Considerations for Component Modeling; 16. Modeling Component Centric Features; 17. Testbenches for Component Models. Application-specific integrated circuits. http://id.loc.gov/authorities/subjects/sh89004045 Field programmable gate arrays. http://id.loc.gov/authorities/subjects/sh93009062 Circuits intégrés à la demande. Réseaux logiques programmables par l'utilisateur. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits Logic. bisacsh COMPUTERS Logic Design. bisacsh Application specific integrated circuits. cct Field programmable gate arrays fast Application-specific integrated circuits fast |
| subject_GND | http://id.loc.gov/authorities/subjects/sh89004045 http://id.loc.gov/authorities/subjects/sh93009062 |
| title | ASIC and FPGA verification : a guide to component modeling / |
| title_auth | ASIC and FPGA verification : a guide to component modeling / |
| title_exact_search | ASIC and FPGA verification : a guide to component modeling / |
| title_full | ASIC and FPGA verification : a guide to component modeling / Richard Munden. |
| title_fullStr | ASIC and FPGA verification : a guide to component modeling / Richard Munden. |
| title_full_unstemmed | ASIC and FPGA verification : a guide to component modeling / Richard Munden. |
| title_short | ASIC and FPGA verification : |
| title_sort | asic and fpga verification a guide to component modeling |
| title_sub | a guide to component modeling / |
| topic | Application-specific integrated circuits. http://id.loc.gov/authorities/subjects/sh89004045 Field programmable gate arrays. http://id.loc.gov/authorities/subjects/sh93009062 Circuits intégrés à la demande. Réseaux logiques programmables par l'utilisateur. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits Logic. bisacsh COMPUTERS Logic Design. bisacsh Application specific integrated circuits. cct Field programmable gate arrays fast Application-specific integrated circuits fast |
| topic_facet | Application-specific integrated circuits. Field programmable gate arrays. Circuits intégrés à la demande. Réseaux logiques programmables par l'utilisateur. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. TECHNOLOGY & ENGINEERING Electronics Circuits Logic. COMPUTERS Logic Design. Application specific integrated circuits. Field programmable gate arrays Application-specific integrated circuits |
| url | https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=117163 https://www.sciencedirect.com/science/book/9780125105811 |
| work_keys_str_mv | AT mundenrichard asicandfpgaverificationaguidetocomponentmodeling |