Verilog HDL design examples:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boca Raton
CRC Press, Taylor & Francis Group
[2017]
|
| Schlagworte: | |
| Online-Zugang: | URL des Erstveröffentlichers |
| Beschreibung: | 1 Online-Ressource (xv, 655 Seiten) Illustrationen |
| ISBN: | 9781315103846 |
| DOI: | 10.1201/b22315 |
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Datensatz im Suchindex
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| adam_text | |
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| author | Cavanagh, Joseph J. F. |
| author_facet | Cavanagh, Joseph J. F. |
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1201/b22315 |
| format | Electronic eBook |
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| id | DE-604.BV050156392 |
| illustrated | Illustrated |
| indexdate | 2025-02-06T15:00:40Z |
| institution | BVB |
| isbn | 9781315103846 |
| language | English |
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| physical | 1 Online-Ressource (xv, 655 Seiten) Illustrationen |
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| publishDate | 2017 |
| publishDateSearch | 2017 |
| publishDateSort | 2017 |
| publisher | CRC Press, Taylor & Francis Group |
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| spelling | Cavanagh, Joseph J. F. Verfasser aut Verilog HDL design examples Joseph Cavanagh Boca Raton CRC Press, Taylor & Francis Group [2017] © 2017 1 Online-Ressource (xv, 655 Seiten) Illustrationen txt rdacontent c rdamedia cr rdacarrier VERILOG (DE-588)4268385-3 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf VERILOG (DE-588)4268385-3 s VHDL (DE-588)4254792-1 s DE-604 Erscheint auch als Druck-Ausgabe 978-1-138-09995-1 https://doi.org/10.1201/b22315 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Cavanagh, Joseph J. F. Verilog HDL design examples VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd |
| subject_GND | (DE-588)4268385-3 (DE-588)4254792-1 |
| title | Verilog HDL design examples |
| title_auth | Verilog HDL design examples |
| title_exact_search | Verilog HDL design examples |
| title_full | Verilog HDL design examples Joseph Cavanagh |
| title_fullStr | Verilog HDL design examples Joseph Cavanagh |
| title_full_unstemmed | Verilog HDL design examples Joseph Cavanagh |
| title_short | Verilog HDL design examples |
| title_sort | verilog hdl design examples |
| topic | VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd |
| topic_facet | VERILOG VHDL |
| url | https://doi.org/10.1201/b22315 |
| work_keys_str_mv | AT cavanaghjosephjf veriloghdldesignexamples |