RISC-V assembly language programming: using ESP32-C3 and QEMU
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Susteren, the Netherlands ; [Aachen]
Elektor
[2022]
|
| Schriftenreihe: | Elector books
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis Inhaltsverzeichnis |
| Beschreibung: | 268 Seiten Illustrationen 24 cm |
| ISBN: | 9783895765254 3895765252 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV049779022 | ||
| 003 | DE-604 | ||
| 005 | 20240730 | ||
| 007 | t | ||
| 008 | 240712s2022 ne a||| |||| 00||| eng d | ||
| 015 | |a 22,N47 |2 dnb | ||
| 015 | |a 24,A08 |2 dnb | ||
| 016 | 7 | |a 1273086708 |2 DE-101 | |
| 020 | |a 9783895765254 |c Broschur : EUR 39.95 (DE) (freier Preis), EUR 41.10 (AT) (freier Preis), CHF 38.95 (freier Preis) |9 978-3-89576-525-4 | ||
| 020 | |a 3895765252 |9 3-89576-525-2 | ||
| 024 | 3 | |a 9783895765254 | |
| 028 | 5 | 2 | |a Bestellnummer: 20296 |
| 035 | |a (OCoLC)1350538613 | ||
| 035 | |a (DE-599)DNB1273086708 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 044 | |a ne |c XA-NL |a gw |c XA-DE-NW | ||
| 049 | |a DE-83 | ||
| 082 | 0 | 4 | |a 621.3916 |2 23/ger |
| 084 | |a ZN 4980 |0 (DE-625)157428: |2 rvk | ||
| 084 | |8 2\p |a 004 |2 23sdnb | ||
| 084 | |8 1\p |a 621.3 |2 23sdnb | ||
| 100 | 1 | |a Gay, Warren W. |e Verfasser |0 (DE-588)1089695519 |4 aut | |
| 245 | 1 | 0 | |a RISC-V assembly language programming |b using ESP32-C3 and QEMU |c Warren Gay |
| 264 | 1 | |a Susteren, the Netherlands ; [Aachen] |b Elektor |c [2022] | |
| 264 | 4 | |c © 2022 | |
| 300 | |a 268 Seiten |b Illustrationen |c 24 cm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a Elector books | |
| 650 | 0 | 7 | |a Zweiunddreißig-Bit-Mikroprozessor |0 (DE-588)4238351-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a RISC |0 (DE-588)4191875-7 |2 gnd |9 rswk-swf |
| 653 | |a ESP32 | ||
| 653 | |a Compiler | ||
| 653 | |a Espressif | ||
| 653 | |a RISC-V | ||
| 653 | |a Programming | ||
| 689 | 0 | 0 | |a Zweiunddreißig-Bit-Mikroprozessor |0 (DE-588)4238351-1 |D s |
| 689 | 0 | 1 | |a RISC |0 (DE-588)4191875-7 |D s |
| 689 | 0 | |5 DE-604 | |
| 710 | 2 | |a Elektor Verlag GmbH |0 (DE-588)1065539746 |4 pbl | |
| 776 | 0 | 8 | |i Erscheint auch als |n Online-Ausgabe, PDF |z 978-3-89576-526-1 |
| 856 | 4 | 2 | |m B:DE-101 |q application/pdf |u https://d-nb.info/1273086708/04 |3 Inhaltsverzeichnis |
| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=035120034&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 883 | 2 | |8 1\p |a dnb |d 20231009 |q DE-101 |u https://d-nb.info/provenance/plan#dnb | |
| 883 | 2 | |8 2\p |a dnb |d 20231009 |q DE-101 |u https://d-nb.info/provenance/plan#dnb | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-035120034 | |
Datensatz im Suchindex
| _version_ | 1806142702234894336 |
|---|---|
| adam_text |
CONTENTS
CHAPTER
1
YY
INTRODUCTION
.
13
1.1. THE
JOY
OF
THE
MACHINE
.
13
1.2.
ASSEMBLER
LANGUAGE
.
14
1.3.
WHY
RISC-V?
.
14
1.4.
BASE
INSTRUCTION
SETS
COVERED
.
15
1.5.
PROJECTS
IN
THIS
BOOK
.
15
1.6.
WHAT
DO
YOU
NEED?
.
15
1.6.1.
ESP32-C3
HARDWARE
.
16
1.7.
ASSUMPTIONS
ABOUT
THE
READER
.
18
1.8.
SUMMARY
.
18
CHAPTER
2
YY
ESP32-C3
INSTALLATION
.
19
2.1.
ESP32-C3
DEVICE
.
19
2.2.
MANUAL
INSTALLATION
(LINUX
AND
MACOS)
.
20
2.3.
WINDOWS
INSTALL
.
29
2.4.
SUMMARY
.
34
CHAPTER
3
YY
INSTALLATION
AND
SETUP
OF
QEMU
.
35
3.1.
LINUX/MACOS
PLATFORMS:
.
35
3.2.
WINDOWS
.
36
3.3.
INSTALLING
QEMU
ON
MACOS
.
36
3.4.
INSTALL
QEMU
ON
DEVUAN
LINUX
.
36
3.5.
QEMU
PACKAGE
SEARCH
.
37
3.5.1.
BUILDING
QEMU
ON
LINUX
.
37
3.5.2.
BASIC
BUILD
STEPS
.
38
3.5.3.
LINUX/MACOS
SETUP
OF
FEDORA
LINUX
.
41
3.5.4.
LINUX/MACOS
BOOT
FEDORA
LINUX
.
42
3.5.5.
LINUX/MACOS
BOOT
TEST
.
43
3.6.
INSTALLING
QEMU
ON
WINDOWS
.
46
3.7.
SUMMARY
.
50
CHAPTER
4
YY
ARCHITECTURE
.
51
4.1.
PROGRAM
COUNTER
REGISTER
.
51
RISC-V
ASSEMBLY
LANGUAGE
PROGRAMMING
4.2.
ENDIANNESS
.
51
4.3.
GENERAL
PURPOSE
REGISTERS
.
52
4.4.
INTRODUCING
SUBSETS
.
52
4.5.
REGISTER
SPECIFICS
.
53
4.5.1.
NO
FLAG
BITS
.
54
4.5.2.
REGISTER
XO
/
ZERO
.
55
4.5.3.
REGISTER
XL
/
RA
.
55
4.5.4.
REGISTER
X2
/
SP
.
55
4.5.5.
REGISTER
X3
/
GP
.
55
4.5.6.
REGISTER
X4
/
TP
.
55
4.5.7.
REGISTERS
X5-X7
/
T0-T2
.
55
4.5.8.
REGISTER
X8
/
SO
/
FP
.
55
4.5.9.
REGISTER
X9
/
SL
.
55
4.5.10.
REGISTERS
XLO-XLL
/
AO-AL
.
.55
4.5.11.
REGISTERS
X12-X17
/
A2-A7
.
56
4.5.12.
REGISTERS
XL7-X27
/
S2-SLL
.
56
4.5.13.
REGISTERS
X28-X31
/
T3-T6
.
56
4.5.14.
REGISTER
SUMMARY
.
56
4.6.
INSTRUCTION
SET
BASE
SUBSETS/EXTENSIONS
.
56
4.7.
ESP32-C3
HARDWARE:
.
58
4.8.
QEMU
RISC-V
64
BIT
EMULATOR
.
58
4.9.
RISC-V
PRIVILEGE
LEVELS
.
59
4.10.
RISC-V
IS
HUGE
.
60
4.11.
SUMMARY
.
60
CHAPT
ER
5
YY
GETTING
STARTED
.
61
5.1.
MEMORY
MODELS
&
DATA
TYPES
.
61
5.1.1.
RV32
MODEL
.
61
5.1.2.
RV64
MODEL
.
62
5.2.
THE
IMPACT
OF
XLEN
.
62
5.3.
FIRST
EXERCISE
.
63
5.3.1.
THE
MAIN
PROGRAM
.
63
5.3.2.
ASSEMBLER
ROUTINE
ADD3
.
64
YY
6
CONTENTS
5.3.3.
ASSEMBLY
LANGUAGE
FORMAT
.
64
5.3.4.
PSEUDO
OPCODE
.GLOBAL
.
65
5.3.5.
PSEUDO
OPCODE
.TEXT
.
65
5.3.6.
THE
ADD
OPCODE
.
66
5.3.7.
CALLING
ADD3
.
66
5.3.8.
RV64I
CONSIDERATION
.
67
5.3.9.
RUNNING
THE
DEMONSTRATION
.
.67
5.4.
FIRST
EXERCISE
ON
ESP32-C3
.
68
5.5.
ASSEMBLER
LISTINGS
.
72
5.5.1.
ESP32-C3
ASSEMBLER
LISTING
.
72
5.5.2.
INFLUENCING
ASSEMBLY
CODE
.
73
5.4.3.
OBJDUMP
.
75
5.6.
SUMMARY
.
75
CHAPTER
6
YY
LOAD
AND
STORE
MEMORY
.
76
6.1.
A
WORD
ABOUT
WORD
SIZES
.
76
6.2.
LOAD
INSTRUCTIONS
.
76
6.3.
LOAD
PROGRAM
EXAMPLE
.
77
6.4.
THE
.DATA
SECTION
.
80
6.5.
UNSIGNED
VALUES
.
83
6.6.
MEMORY
ALIGNMENT
.
83
6.7.
EXPERIMENT
.
85
6.8.
IMMEDIATE
VALUES
.
85
6.9.
THE
LI
PSEUDO-OP
.
86
6.10.
THE
ADDI
OPCODE
.
87
6.11.
PSEUDO-OP
MV
.
87
6.12.
LOADS
UNDER
RV64I
.
88
6.1.3
THE
.SECTION
PSEUDO-OP
.
89
6.14.
STORING
DATA
.
90
6.15.
REVIEW
.
94
6.16.
RISC-V
ASSEMBLER
MODIFIERS
.
95
6.17.
SUMMARY
.
95
YY
7
RISC-V
ASSEMBLY
LANGUAGE
PROGRAMMING
CHAPTER
7
YY
CALLING
CONVENTION
.
96
7.1.
REGISTER
USAGE
.
96
7.2.
CALL
PROCEDURE
.
97
7.2.1.
OPCODE
JAL
.
97
7.2.2.
PSEUDO
OPCODE
JR
.
97
7.2.3.
PSEUDO
OPCODE
RET
.
98
7.2.4.
GENERAL
CALL
PROCEDURE
.
98
7.2.5.
CALL
TO
32-BIT
ABSOLUTE
ADDRESS
.
98
7.2.6.
REVISED
CALL
PROCEDURE
.
99
7.2.7.
CONCRETE
CALL
EXAMPLE
.
99
7.2.8.
SIMPLE
CALL
EXPERIMENT
.
100
7.2.9.
RUNNING
IN
GDB
.
101
7.3.
ARGUMENT
PASSING
IN
REGISTERS
.104
7.4.
THE
STACK
.
105
7.4.1.
PROLOGUE
.
105
7.4.2.
EPILOGUE
.
106
7.4.3.
FLOATING
POINT
ARGUMENTS
.
106
7.4.4.
A
BIG
CALL
EXPERIMENT
.
.
106
7.5.
CALLING
PRINTF()
.
ILL
7.6.
SUMMARY
.
114
CHAPTER
8
YY
FLOW
CONTROL
.
116
8.1.
BRANCHING
INSTRUCTIONS
.
116
8.1.1.
UNCONDITIONAL
TRANSFERS
.
116
8.1.2.
CONDITIONAL
BRANCHES
.
117
8.2.
SHIFT
OPCODES
.
117
8.3.
ESP32-C3
PROJECT
.
118
8.3.1.
FUNCTION
C_ONES()
.
119
8.3.2.
MAIN
TEST
PROGRAM
.
119
8.3.3.
ASSEMBLER
FUNCTION
ONES()
.
120
8.4.
COMPARE
AND
SET
.
123
8.5.
ODD
PARITY
EXAMPLE
.
123
YY
8
CONTENTS
8.6.
RV64I
ODD
PARITY
.
125
8.7.
POSITION
INDEPENDENT
CODE
.
128
8.8.
SUMMARY
.
129
CHAPTER
9
YY
BASIC
OPCODES.
.
130
9.1.
ARITHMETIC
OPCODES
.
130
9.1.1.
ADD,
ADDI
AND
SUB
.
130
9.1.2.
LUI
.
130
9.1.3.
AUIPC
.
131
9.1.4.
RV64
ARITHMETIC
.
131
9.2.
LOGICAL
OPCODES
.
131
9.3.
ESP32-C3
ROTATE
LEFT
.
132
9.4.
RV64
ROTATE
LEFT
.
134
9.5.
ESP32-C3
ROTATE
RIGHT
.
136
9.6.
PSEUDO
OPCODES
.
138
9.7.
UNSIGNED
MULTI-PRECISION
ARITHMETIC
.
138
9.8.
SIGNED
MULTI-PRECISION
ARITHMETIC
.
.
140
9.8.1.
SIGNED
OVERFLOW
.
140
9.9.
SUMMARY
.
147
CHAPTER
10
YY
MULTIPLY
/
DIVIDE
.
.
148
10.1.
MULTIPLICATION
OPERATIONS
.
148
10.2.
DIVISION
OPERATIONS
.
149
10.3.
OPCODE
MUL/MULU
.
149
10.4.
OPCODE
MULHS/MULHU
.
149
10.5.
OPTIMIZED
MULTIPLY
.
149
10.6.
UNSIGNED
FACTORIAL
.
151
10.7.
OPCODE
DIV/DIVU
.
153
10.8.
OPTIMIZED
DIVIDE
.
153
10.9
DIVISION
BY
ZERO
.
154
10.10
DIVIDE
OVERFLOW
.
154
10.11
SAFE
DIVISION
.
154
10.12.
GREATEST
COMMON
DIVISOR
.
158
10.13.
COMBINATIONS
.
160
YY
9
RISC-V
ASSEMBLY
LANGUAGE
PROGRAMMING
10.14.
SUMMARY
.
163
CHAPTER
11
YY
ADDRESSING,
SUBSCRIPTING
AND
STRINGS
.
164
11.1.
TESTING
FOR
NULL
POINTERS
.
164
11.2.
SIZEOF
TYPE
FOR
POINTERS
.
164
11.3.
MATRIX
MEMORY
LAYOUT
.
164
11.3.1.
SUBSCRIPT
CALCULATION
.
165
11.4.
IDENTITY
MATRIX
EXAMPLE
.
165
11.5.
STRING
FUNCTIONS
.
169
11.5.1.
FUNCTION
STRLEN()
.
169
11.5.2.
FUNCTION
STRNCPY32()
.
171
11.5.3.
STRING
TO
INTEGER
CONVERSION
.
174
11.5.4.
WHAT
IF
THERE
IS
NO
MULTIPLY?
.
178
11.5.5.
INTEGER
TO
STRING
CONVERSION
.
178
11.6.
INDEXED
BRANCHING
.
181
11.7.
SUMMARY
.
184
CHAPTER
12
YY
FLOATING
POINT
.
185
12.1.
FLOATING
POINT
REGISTERS
.
185
12.2.
GNU
CALLING
CONVENTION
.
186
12.3.
FLOATING-POINT
CONTROL
AND
STATUS
REGISTER
(FCSR)
.
186
12.3.1.
ROUNDING
MODES
FCSR.FRM
.
187
12.3.2.
ACCRUED
EXCEPTION
FLAGS
FCSR.FFLAGS
.
188
12.4.
NAN
GENERATION
AND
PROPAGATION
.
188
12.5.
OPCODES
AND
DATA
FORMATS
.
188
12.6.
LOAD
AND
STORE
.
189
12.7.
FLOATING
COMPUTATION
.
189
12.8.
CONVERSION
OPERATIONS
.
190
12.8.1.
FLOATING-POINT
ZERO
.
190
12.8.2.
CONVERSION
FAILURES
.
191
12.9.
FLOATING-POINT
SIGNS
.
191
12.10.
FLOATING-POINT
MOVE
.
192
12.11.
FLOATING-POINT
COMPARE
.
192
12.12.
CLASSIFY
OPERATION
.
192
YY
10
CONTENTS
12.13.
FAHRENHEIT
TO
CELSIUS
REVISITED
.
193
12.14.
SUMMARY
.
196
CHAPTER
13
YY
PORTABILITY
.
197
13.1.
C/C++
PRE-PROCESSOR
.
197
13.2.
TESTING
FOR
RISC-V
ARCHITECTURE
.
199
13.3.
TESTING
FOR
INTEGER
MULTIPLICATION
.
199
13.4.
RV32
VS
RV64
.
202
13.5.
ASSEMBLER
MACROS
.204
13.6.
SUMMARY
.
208
CHAPTER
14
YY
DETERMINING
SUPPORT
.
209
14.1.
PRIVILEGE
LEVELS
.209
14.1.1.
MACHINE
LEVEL
.
210
14.1.2.
SUPERVISOR
LEVEL
.210
14.1.3.
USER
LEVEL
.
210
14.2.
CONTROL
AND
STATUS
REGISTERS
.
210
14.2.1.
MACHINE
ISA
REGISTER
.
210
14.3.
OPCODES
.
212
14.4.
ESP32-C3
.
212
14.5.
REPORTING
MISA
.
.
212
14.6.
RV64
PLATFORM
.216
14.7.
COUNTERS
.
219
14.7.1
PROJECT
RDCYCLE
.
219
14.7.2
.
ESP32-C3
RDCYCLE
SUPPORT
.
222
14.8.
SUMMARY
.
225
CHAPTER
15
YY
JTAG
DEBUGGING
.
226
15.1.
ESPRESSIF
JTAG
.
226
15.2.
DEVICE
REQUIREMENTS
.
226
15.3.
SOFTWARE
COMPONENTS
.227
15.4.
JTAG
WITH
NO
SERIAL
WINDOW
.
228
15.4.1.
STARTING
OPENOCD
.
229
15.4.2.
PROBLEMS
WITH
OPENOCD
.
230
15.4.3.
TERMINATING
OPENOCD
.
YY
YY
230
YY
11
RISC-V
ASSEMBLY
LANGUAGE
PROGRAMMING
15.4.4.
START
GDB
.230
15.5.
OPERATING
GDB
.232
15.5.1.
ABBREVIATIONS
.232
15.5.2
GDB
WALKTHROUGH
.233
15.5.3.
QUITTING
GDB
.240
15.6.
JTAG
WITH
A
SERIAL
WINDOW
.
241
15.6.
MISCELLANEOUS
.
244
15.7.
SUMMARY
.
244
CHAPTER
16
YY
INLINE
ASSEMBLY
.
246
16.1.
KEYWORD
ASM
.246
16.2.
BASIC
ASM
FORM
.246
16.2.1.
KEYWORD
VOLATILE
.
248
16.2.2.
MULTIPLE
INSTRUCTIONS
.
248
16.2.3.
BEHIND
THE
SCENES
.
249
16.3.
EXTENDED
ASM
.
249
16.3.1.
ASSEMBLER
TEMPLATE
.
249
16.3.2.
OUTPUT
OPERANDS
.
250
16.3.2.1.
CONSTRAINT
.
250
16.3.3.
INPUT
OPERANDS
.253
16.3.3.1.
CLOBBERS
.
254
16.4.
BIT
MULTIPLY
.255
16.5.
EXAMPLE
ASM
GOTO
.257
16.6.
REGISTER
CONSTRAINTS
.
259
16.7.
SUMMARY
.265
INDEX
.
266
YY
12 |
| any_adam_object | 1 |
| author | Gay, Warren W. |
| author_GND | (DE-588)1089695519 |
| author_facet | Gay, Warren W. |
| author_role | aut |
| author_sort | Gay, Warren W. |
| author_variant | w w g ww wwg |
| building | Verbundindex |
| bvnumber | BV049779022 |
| classification_rvk | ZN 4980 |
| ctrlnum | (OCoLC)1350538613 (DE-599)DNB1273086708 |
| dewey-full | 621.3916 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3916 |
| dewey-search | 621.3916 |
| dewey-sort | 3621.3916 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV049779022 |
| illustrated | Illustrated |
| indexdate | 2024-08-01T00:25:06Z |
| institution | BVB |
| institution_GND | (DE-588)1065539746 |
| isbn | 9783895765254 3895765252 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-035120034 |
| oclc_num | 1350538613 |
| open_access_boolean | |
| owner | DE-83 |
| owner_facet | DE-83 |
| physical | 268 Seiten Illustrationen 24 cm |
| publishDate | 2022 |
| publishDateSearch | 2022 |
| publishDateSort | 2022 |
| publisher | Elektor |
| record_format | marc |
| series2 | Elector books |
| spelling | Gay, Warren W. Verfasser (DE-588)1089695519 aut RISC-V assembly language programming using ESP32-C3 and QEMU Warren Gay Susteren, the Netherlands ; [Aachen] Elektor [2022] © 2022 268 Seiten Illustrationen 24 cm txt rdacontent n rdamedia nc rdacarrier Elector books Zweiunddreißig-Bit-Mikroprozessor (DE-588)4238351-1 gnd rswk-swf RISC (DE-588)4191875-7 gnd rswk-swf ESP32 Compiler Espressif RISC-V Programming Zweiunddreißig-Bit-Mikroprozessor (DE-588)4238351-1 s RISC (DE-588)4191875-7 s DE-604 Elektor Verlag GmbH (DE-588)1065539746 pbl Erscheint auch als Online-Ausgabe, PDF 978-3-89576-526-1 B:DE-101 application/pdf https://d-nb.info/1273086708/04 Inhaltsverzeichnis DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=035120034&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p dnb 20231009 DE-101 https://d-nb.info/provenance/plan#dnb 2\p dnb 20231009 DE-101 https://d-nb.info/provenance/plan#dnb |
| spellingShingle | Gay, Warren W. RISC-V assembly language programming using ESP32-C3 and QEMU Zweiunddreißig-Bit-Mikroprozessor (DE-588)4238351-1 gnd RISC (DE-588)4191875-7 gnd |
| subject_GND | (DE-588)4238351-1 (DE-588)4191875-7 |
| title | RISC-V assembly language programming using ESP32-C3 and QEMU |
| title_auth | RISC-V assembly language programming using ESP32-C3 and QEMU |
| title_exact_search | RISC-V assembly language programming using ESP32-C3 and QEMU |
| title_full | RISC-V assembly language programming using ESP32-C3 and QEMU Warren Gay |
| title_fullStr | RISC-V assembly language programming using ESP32-C3 and QEMU Warren Gay |
| title_full_unstemmed | RISC-V assembly language programming using ESP32-C3 and QEMU Warren Gay |
| title_short | RISC-V assembly language programming |
| title_sort | risc v assembly language programming using esp32 c3 and qemu |
| title_sub | using ESP32-C3 and QEMU |
| topic | Zweiunddreißig-Bit-Mikroprozessor (DE-588)4238351-1 gnd RISC (DE-588)4191875-7 gnd |
| topic_facet | Zweiunddreißig-Bit-Mikroprozessor RISC |
| url | https://d-nb.info/1273086708/04 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=035120034&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT gaywarrenw riscvassemblylanguageprogrammingusingesp32c3andqemu AT elektorverlaggmbh riscvassemblylanguageprogrammingusingesp32c3andqemu |
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