Completion detection in asynchronous circuits: Toward solution of clock-related design challenges
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Cham
Springer
[2022]
|
| Schlagworte: | |
| Beschreibung: | xv, 119 Seiten Illustrationen (teilweise farbig) |
| ISBN: | 9783031183966 |
Internformat
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| 650 | 4 | |a Electronic circuit design | |
| 650 | 4 | |a Microprocessors | |
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Datensatz im Suchindex
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| id | DE-604.BV049589431 |
| illustrated | Illustrated |
| index_date | 2024-07-03T23:33:08Z |
| indexdate | 2024-07-10T10:11:29Z |
| institution | BVB |
| isbn | 9783031183966 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-034934138 |
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| physical | xv, 119 Seiten Illustrationen (teilweise farbig) |
| publishDate | 2022 |
| publishDateSearch | 2022 |
| publishDateSort | 2022 |
| publisher | Springer |
| record_format | marc |
| spelling | Srivastava, Pallavi Verfasser aut Completion detection in asynchronous circuits Toward solution of clock-related design challenges Pallavi Srivastava Cham Springer [2022] © 2022 xv, 119 Seiten Illustrationen (teilweise farbig) txt rdacontent n rdamedia nc rdacarrier Electronic Circuits and Systems Electronics Design and Verification Processor Architectures Electronic circuits Electronic circuit design Microprocessors Computer architecture Erscheint auch als Online-Ausgabe 978-3-031-18397-3 |
| spellingShingle | Srivastava, Pallavi Completion detection in asynchronous circuits Toward solution of clock-related design challenges Electronic Circuits and Systems Electronics Design and Verification Processor Architectures Electronic circuits Electronic circuit design Microprocessors Computer architecture |
| title | Completion detection in asynchronous circuits Toward solution of clock-related design challenges |
| title_auth | Completion detection in asynchronous circuits Toward solution of clock-related design challenges |
| title_exact_search | Completion detection in asynchronous circuits Toward solution of clock-related design challenges |
| title_exact_search_txtP | Completion detection in asynchronous circuits Toward solution of clock-related design challenges |
| title_full | Completion detection in asynchronous circuits Toward solution of clock-related design challenges Pallavi Srivastava |
| title_fullStr | Completion detection in asynchronous circuits Toward solution of clock-related design challenges Pallavi Srivastava |
| title_full_unstemmed | Completion detection in asynchronous circuits Toward solution of clock-related design challenges Pallavi Srivastava |
| title_short | Completion detection in asynchronous circuits |
| title_sort | completion detection in asynchronous circuits toward solution of clock related design challenges |
| title_sub | Toward solution of clock-related design challenges |
| topic | Electronic Circuits and Systems Electronics Design and Verification Processor Architectures Electronic circuits Electronic circuit design Microprocessors Computer architecture |
| topic_facet | Electronic Circuits and Systems Electronics Design and Verification Processor Architectures Electronic circuits Electronic circuit design Microprocessors Computer architecture |
| work_keys_str_mv | AT srivastavapallavi completiondetectioninasynchronouscircuitstowardsolutionofclockrelateddesignchallenges |