Artificial intelligence applications and reconfigurable architectures:
Cover -- Title Page -- Copyright Page -- Contents -- Preface -- Chapter 1 Strategic Infrastructural Developments to Reinforce Reconfigurable Computing for Indigenous AI Applications -- 1.1 Introduction -- 1.2 Infrastructural Requirements for AI -- 1.3 Categories in AI Hardware -- 1.3.1 Comparing Har...
Gespeichert in:
Weitere Verfasser: | , |
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Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Hoboken, NJ, USA
Wiley
2023
Beverly, MA, USA Scrivener Publishing 2023 |
Schlagworte: | |
Online-Zugang: | FWS01 FWS02 |
Zusammenfassung: | Cover -- Title Page -- Copyright Page -- Contents -- Preface -- Chapter 1 Strategic Infrastructural Developments to Reinforce Reconfigurable Computing for Indigenous AI Applications -- 1.1 Introduction -- 1.2 Infrastructural Requirements for AI -- 1.3 Categories in AI Hardware -- 1.3.1 Comparing Hardware for Artificial Intelligence -- 1.4 Hardware AI Accelerators to Support RC -- 1.4.1 Computing Support for AI Application: Reconfigurable Computing to Foster the Adaptation -- 1.4.2 Reconfiguration Computing Model -- 1.4.3 Reconfigurable Computing Model as an Accelerator -- 1.5 Architecture and Accelerator for AI-Based Applications -- 1.5.1 Advantages of Reconfigurable Computing Accelerators -- 1.5.2 Disadvantages of Reconfigurable Computing Accelerators -- 1.6 Conclusion -- References -- Chapter 2 Review of Artificial Intelligence Applications and Architectures -- 2.1 Introduction -- 2.2 Technological Platforms for AI Implementation-Graphics Processing Unit -- 2.3 Technological Platforms for AI Implementation-Field Programmable Gate Array (FPGA) -- 2.3.1 Xilinx Zynq -- 2.3.2 Stratix 10 NX Architecture -- 2.4 Design Implementation Aspects -- 2.5 Conclusion -- References -- Chapter 3 An Organized Literature Review on Various Cubic Root Algorithmic Practices for Developing Efficient VLSI Computing System-Understanding Complexity -- 3.1 Introduction -- 3.2 Motivation -- 3.3 Numerous Cubic Root Methods for Emergent VLSI Computing System-Extraction -- 3.4 Performance Study and Discussion -- 3.5 Further Research -- 3.6 Conclusion -- References -- Chapter 4 An Overview of the Hierarchical Temporal Memory Accelerators -- 4.1 Introduction -- 4.2 An Overview of Hierarchical Temporal Memory -- 4.3 HTM on Edge -- 4.4 Digital Accelerators -- 4.4.1 PIM HTM -- 4.4.2 PEN HTM -- 4.4.3 Classic -- 4.5 Analog and Mixed-Signal Accelerators -- 4.5.1 RCN HTM. |
Beschreibung: | Description based on publisher supplied metadata and other sources |
Beschreibung: | 1 Online-Ressource (xvi, 218 Seiten) |
ISBN: | 9781119857891 |
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520 | 3 | |a Cover -- Title Page -- Copyright Page -- Contents -- Preface -- Chapter 1 Strategic Infrastructural Developments to Reinforce Reconfigurable Computing for Indigenous AI Applications -- 1.1 Introduction -- 1.2 Infrastructural Requirements for AI -- 1.3 Categories in AI Hardware -- 1.3.1 Comparing Hardware for Artificial Intelligence -- 1.4 Hardware AI Accelerators to Support RC -- 1.4.1 Computing Support for AI Application: Reconfigurable Computing to Foster the Adaptation -- 1.4.2 Reconfiguration Computing Model -- 1.4.3 Reconfigurable Computing Model as an Accelerator -- 1.5 Architecture and Accelerator for AI-Based Applications -- 1.5.1 Advantages of Reconfigurable Computing Accelerators -- 1.5.2 Disadvantages of Reconfigurable Computing Accelerators -- 1.6 Conclusion -- References -- Chapter 2 Review of Artificial Intelligence Applications and Architectures -- 2.1 Introduction -- 2.2 Technological Platforms for AI Implementation-Graphics Processing Unit -- 2.3 Technological Platforms for AI Implementation-Field Programmable Gate Array (FPGA) -- 2.3.1 Xilinx Zynq -- 2.3.2 Stratix 10 NX Architecture -- 2.4 Design Implementation Aspects -- 2.5 Conclusion -- References -- Chapter 3 An Organized Literature Review on Various Cubic Root Algorithmic Practices for Developing Efficient VLSI Computing System-Understanding Complexity -- 3.1 Introduction -- 3.2 Motivation -- 3.3 Numerous Cubic Root Methods for Emergent VLSI Computing System-Extraction -- 3.4 Performance Study and Discussion -- 3.5 Further Research -- 3.6 Conclusion -- References -- Chapter 4 An Overview of the Hierarchical Temporal Memory Accelerators -- 4.1 Introduction -- 4.2 An Overview of Hierarchical Temporal Memory -- 4.3 HTM on Edge -- 4.4 Digital Accelerators -- 4.4.1 PIM HTM -- 4.4.2 PEN HTM -- 4.4.3 Classic -- 4.5 Analog and Mixed-Signal Accelerators -- 4.5.1 RCN HTM. | |
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id | DE-604.BV049484084 |
illustrated | Not Illustrated |
index_date | 2024-07-03T23:18:35Z |
indexdate | 2024-08-01T11:06:51Z |
institution | BVB |
isbn | 9781119857891 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-034829504 |
oclc_num | 1418698110 |
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owner_facet | DE-863 DE-BY-FWS DE-862 DE-BY-FWS |
physical | 1 Online-Ressource (xvi, 218 Seiten) |
psigel | ZDB-35-WIC |
publishDate | 2023 |
publishDateSearch | 2023 |
publishDateSort | 2023 |
publisher | Wiley Scrivener Publishing |
record_format | marc |
spellingShingle | Artificial intelligence applications and reconfigurable architectures |
title | Artificial intelligence applications and reconfigurable architectures |
title_auth | Artificial intelligence applications and reconfigurable architectures |
title_exact_search | Artificial intelligence applications and reconfigurable architectures |
title_exact_search_txtP | Artificial intelligence applications and reconfigurable architectures |
title_full | Artificial intelligence applications and reconfigurable architectures edited by Anuradha D. Thakare and Sheetal Umesh Bhandari |
title_fullStr | Artificial intelligence applications and reconfigurable architectures edited by Anuradha D. Thakare and Sheetal Umesh Bhandari |
title_full_unstemmed | Artificial intelligence applications and reconfigurable architectures edited by Anuradha D. Thakare and Sheetal Umesh Bhandari |
title_short | Artificial intelligence applications and reconfigurable architectures |
title_sort | artificial intelligence applications and reconfigurable architectures |
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