Cover -- Title Page -- Copyright Page -- Contents -- Preface -- Chapter 1 Strategic Infrastructural Developments to Reinforce Reconfigurable Computing for Indigenous AI Applications -- 1.1 Introduction -- 1.2 Infrastructural Requirements for AI -- 1.3 Categories in AI Hardware -- 1.3.1 Comparing Har...

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Bibliographische Detailangaben

Weitere Verfasser:	Thakare, Anuradha D. 1978- (HerausgeberIn), Bhandari, Sheetal Umesh (HerausgeberIn)
Format:	Elektronisch E-Book
Sprache:	English
Veröffentlicht:	Hoboken, NJ, USA Wiley 2023 Beverly, MA, USA Scrivener Publishing 2023
Schlagworte:	Electronic books
Online-Zugang:	FWS01 FWS02
Zusammenfassung:	Cover -- Title Page -- Copyright Page -- Contents -- Preface -- Chapter 1 Strategic Infrastructural Developments to Reinforce Reconfigurable Computing for Indigenous AI Applications -- 1.1 Introduction -- 1.2 Infrastructural Requirements for AI -- 1.3 Categories in AI Hardware -- 1.3.1 Comparing Hardware for Artificial Intelligence -- 1.4 Hardware AI Accelerators to Support RC -- 1.4.1 Computing Support for AI Application: Reconfigurable Computing to Foster the Adaptation -- 1.4.2 Reconfiguration Computing Model -- 1.4.3 Reconfigurable Computing Model as an Accelerator -- 1.5 Architecture and Accelerator for AI-Based Applications -- 1.5.1 Advantages of Reconfigurable Computing Accelerators -- 1.5.2 Disadvantages of Reconfigurable Computing Accelerators -- 1.6 Conclusion -- References -- Chapter 2 Review of Artificial Intelligence Applications and Architectures -- 2.1 Introduction -- 2.2 Technological Platforms for AI Implementation-Graphics Processing Unit -- 2.3 Technological Platforms for AI Implementation-Field Programmable Gate Array (FPGA) -- 2.3.1 Xilinx Zynq -- 2.3.2 Stratix 10 NX Architecture -- 2.4 Design Implementation Aspects -- 2.5 Conclusion -- References -- Chapter 3 An Organized Literature Review on Various Cubic Root Algorithmic Practices for Developing Efficient VLSI Computing System-Understanding Complexity -- 3.1 Introduction -- 3.2 Motivation -- 3.3 Numerous Cubic Root Methods for Emergent VLSI Computing System-Extraction -- 3.4 Performance Study and Discussion -- 3.5 Further Research -- 3.6 Conclusion -- References -- Chapter 4 An Overview of the Hierarchical Temporal Memory Accelerators -- 4.1 Introduction -- 4.2 An Overview of Hierarchical Temporal Memory -- 4.3 HTM on Edge -- 4.4 Digital Accelerators -- 4.4.1 PIM HTM -- 4.4.2 PEN HTM -- 4.4.3 Classic -- 4.5 Analog and Mixed-Signal Accelerators -- 4.5.1 RCN HTM.
Beschreibung:	Description based on publisher supplied metadata and other sources
Beschreibung:	1 Online-Ressource (xvi, 218 Seiten)
ISBN:	9781119857891