Invasive computing:
Gespeichert in:
| Weitere Verfasser: | |
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| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Erlangen
FAU University Press
2022
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| Schlagworte: | |
| Online-Zugang: | Volltext Volltext Volltext Volltext Inhaltsverzeichnis |
| Beschreibung: | ix, 431 Seiten Illustrationen, Diagramme 24 cm x 17 cm, 1067 g |
| ISBN: | 9783961475704 3961475709 9783961475711 |
| DOI: | 10.25593/978-3-96147-571-1 |
Internformat
MARC
| LEADER | 00000nam a22000008c 4500 | ||
|---|---|---|---|
| 001 | BV048451107 | ||
| 003 | DE-604 | ||
| 005 | 20241025 | ||
| 007 | t | ||
| 008 | 220901s2022 gw a||| |||| 00||| eng d | ||
| 015 | |a 22,N35 |2 dnb | ||
| 016 | 7 | |a 1266112472 |2 DE-101 | |
| 020 | |a 9783961475704 |c Broschur: EUR 54.50 (DE), EUR 56.10 (AT) |9 978-3-96147-570-4 | ||
| 020 | |a 3961475709 |9 3-96147-570-9 | ||
| 020 | |a 9783961475711 |c OnlineAusgabe |9 978-3-96147-571-1 | ||
| 024 | 3 | |a 9783961475704 | |
| 035 | |a (OCoLC)1343010421 | ||
| 035 | |a (DE-599)DNB1266112472 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 044 | |a gw |c XA-DE-BY | ||
| 049 | |a DE-29 |a DE-12 |a DE-29T |a DE-860 |a DE-91 | ||
| 084 | |8 1\p |a 004 |2 23sdnb | ||
| 245 | 1 | 0 | |a Invasive computing |c Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Eds.) |
| 246 | 1 | 3 | |a Invasives Rechnen |
| 264 | 1 | |a Erlangen |b FAU University Press |c 2022 | |
| 300 | |a ix, 431 Seiten |b Illustrationen, Diagramme |c 24 cm x 17 cm, 1067 g | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a Datenverarbeitungssystem |0 (DE-588)4125229-9 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Parallelverarbeitung |0 (DE-588)4075860-6 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Programmierung |0 (DE-588)4076370-5 |2 gnd |9 rswk-swf |
| 653 | |a Parallelprogrammierung | ||
| 653 | |a Dienstgüte | ||
| 653 | |a Network-on-Chip | ||
| 653 | |a Chip-Multiprozessor | ||
| 653 | |a System-on-Chip | ||
| 653 | |a Parallelverarbeitung | ||
| 653 | |a Ressourcenverwaltung | ||
| 653 | |a Hardwarebeschleunigung | ||
| 653 | |a Ablaufplanung | ||
| 653 | |a Parallel Computing | ||
| 653 | |a Multicore Computer Architecture | ||
| 653 | |a Resource-aware Programming | ||
| 653 | |a Run-time Systems | ||
| 653 | |a Compilation | ||
| 689 | 0 | 0 | |a Datenverarbeitungssystem |0 (DE-588)4125229-9 |D s |
| 689 | 0 | 1 | |a Parallelverarbeitung |0 (DE-588)4075860-6 |D s |
| 689 | 0 | 2 | |a Programmierung |0 (DE-588)4076370-5 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Teich, Jürgen |d 1964- |0 (DE-588)113591942 |4 edt | |
| 710 | 2 | |a FAU University Press ein Imprint der Universität Erlangen-Nürnberg |b Universitätsbibliothek |0 (DE-588)1068111240 |4 pbl | |
| 776 | 0 | 8 | |i Erscheint auch als |n Online-Ausgabe |t Invasive Computing |d Erlangen : FAU University Press, 2022 |h Online-Ressource |z 978-3-96147-571-1 |
| 776 | 0 | 8 | |i Erscheint auch als |n Online-Ausgabe |o 10.25593/978-3-96147-571-1 |o urn:nbn:de:bvb:29-opus4-200331 |
| 856 | 4 | 1 | |u https://open.fau.de/handle/openfau/20033 |x Verlag |z kostenfrei |3 Volltext |
| 856 | 4 | 1 | |u https://doi.org/10.25593/978-3-96147-571-1 |x Resolving-System |z kostenfrei |3 Volltext |
| 856 | 4 | 1 | |u https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-200331 |x Resolving-System |z kostenfrei |3 Volltext |
| 856 | 4 | 1 | |u https://d-nb.info/1266414916/34 |x Langzeitarchivierung Nationalbibliothek |z kostenfrei |3 Volltext |
| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=033829258&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 883 | 1 | |8 1\p |a vlb |d 20220823 |q DE-101 |u https://d-nb.info/provenance/plan#vlb | |
| 912 | |a ebook | ||
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-033829258 | |
Datensatz im Suchindex
| _version_ | 1813887256564334592 |
|---|---|
| adam_text |
CONTENTS
I
INTRODUCTION
TO
INVASIVE
COMPUTING
I
JIIRGEN
TEICH,
JORG
HENKEL,
ANDREAS
HERKERSDORF
1.1
WHAT
IS
INVASIVE
COMPUTING?
.
2
1.2
LONG-TERM
RESEARCH
GOALS
AND
VISION
.
6
1.3
ACHIEVEMENTS
IN
FIRST
AND
SECOND
FUNDING
PHASES
(2010-2018)
.
.
13
1.4
ASSESSMENT
OF
PROJECT
STRUCTURE
.
41
1.5
RESEARCH
FOCUS
IN
THE
THIRD
FUNDING
PHASE
(2018-2022)
.
43
1.5.1
GOALS
AND
STRATEGY
.
43
1.5.2
RESEARCH
FOCUS
PER
PROJECT
AREA
.
44
1.5.3
INVASIC
VALIDATION
AND
DEMONSTRATOR
ROAD
MAP
.
53
1.5.4
WORKING
GROUPS
-
DEVELOPING
CROSS-PROJECT
SYNERGIES
.
.
55
A:
FUNDAMENTALS,
LANGUAGE
AND
ALGORITHM
RESEARCH
69
2
BASICS
OF
INVASIVE
COMPUTING
69
JIIRGEN
TEICH,
KHALIL
ESPER,
JOACHIM
FALK,
BEHNAZ
POURMOHSENI,
TOBIAS
SCHWARZER,
STEFAN
WILDERMANN
2.1
RUN-TIME
REQUIREMENT
ENFORCEMENT
(RRE)
.
69
2.2
TAXONOMY
OF
RUN-TIME
REQUIREMENT
ENFORCERS
.
71
2.3
APPLICATION
CHARACTERISATION
AND
ENFORCEMENT
ACTIONS
.
73
2.4
POWER,
LATENCY,
AND
ENERGY
MODEL
.
74
2.5
ENERGY-MINIMISED
TIMING
ENFORCEMENT
.
77
2.6
DISTRIBUTED
ENFORCEMENT
.
78
2.7
FEEDBACK-BASED
ENFORCEMENT
STRATEGIES
.
81
2.7.1
FORMAL
DEFINITIONS
.
82
2.7.2
VERIFICATION
GOALS
.
85
2.7.3
PROPERTY
SPECIFICATION
IN
PRISM
.
87
2.7.4
VERIFICATION
RESULTS
.
88
2.8
CONCLUSIONS
AND
ACKNOWLEDGEMENT
.
92
3
CHARACTERISATION
AND
ANALYSIS
OF
INVASIVE
ALGORITHMIC
PATTERNS
97
MICHAEL
BADER,
STEFAN
WILDERMANN,
MICHAEL
GLAFI,
ALEXANDER
POPPI,
BEHNAZ
POURMOHSENI,
TOBIAS
SCHWARZER,
JAN
SPIECK,
MARIO
WILLE
3.1
INTRODUCTION
.
97
3.2
ALGORITHMIC
PATTERNS
.
98
3.2.1
THE
SHALLOW
WATER
EQUATIONS
.
98
3.2.2
SWE-X10
.
100
III
3.3
HYBRID
APPLICATION
MAPPING
.
105
3.3.1
COMPLEXITY
REDUCTION
.
107
3.3.2
COMPOSABILITY
.
108
3.3.3
MAPPING
RECONFIGURATION
AND
TASK
MIGRATION
.
109
3.3.4
SCENARIO-AWARE
HAM
.
109
3.4
CONCLUSIONS
AND
ACKNOWLEDGEMENTS
.
119
4
SCHEDULING
INVASIVE
MULTICORE
PROGRAMS
UNDER
UNCERTAINTY
123
NICOLE
MEGOW,
ALEXANDER
LINDERMAYR,
BERTRAND
SIMON
4.1
INTRODUCTION
.
123
4.2
UNCERTAIN
EXECUTION
TIMES
.
124
4.2.1
LEARNING-AUGMENTED
ALGORITHM
DESIGN
.
125
4.2.2
PREDICTION
MODEL
AND
ERROR
DEFINITION
.
127
4.2.3
THE
PREFERENTIAL
TIME
SHARING
FRAMEWORK
.
129
4.2.4
EXPERIMENTAL
EVALUATION
.
131
4.3
UNCERTAIN
TASK
GRAPHS
.
135
4.4
UNCERTAIN
PROCESSOR
AVAILABILITY
OR
SPEED
.
139
4.5
SPEED-SCALING
FOR
RUN-TIME
REQUIREMENT
ENFORCEMENT
AND
POWER
MANAGEMENT
.
142
4.6
CONCLUSION
.
145
B:
ARCHITECTURAL
RESEARCH
151
5
ADAPTIVE
APPLICATION-SPECIFIC
INVASIVE
MICRO-ARCHITECTURES
151
LARS
BAUER,
JIIRGEN
BECKER,
JORG
HENKEL,
FABIAN
LESNIAK,
HASSAN
NASSAR
5.1
INTRODUCTION
.
151
5.1.1
OVERVIEW
OF
THE
Z-CORE
ARCHITECTURE
.
152
5.1.2
PROTOTYPE
AND
INTEGRATION
.
154
5.2
GENERATING
AND
USING
SPECIAL
INSTRUCTIONS
(SIS)
.
154
5.2.1
EXAMPLES
FOR
SIS
AND
ACCELERATORS
.
155
5.2.2
AUTOMATIC
GENERATION
OF
SIS
DURING
RUNTIME
.
157
5.3
RUN-TIME
ADAPTIVE
CACHE
ARCHITECTURES
.
158
5.3.1
INTRA-TILE
CACHE
RE-ALLOCATION
.
158
5.3.2
ASSOCIATIVITY
AND
CACHE
SIZE
IMPACT
.
159
5.4
SECURITY
ASPECTS
OF
THE
Z-CORE
.
161
5.4.1
INFORMATION
LEAKAGE
PROTECTION
.
161
5.4.2
ISOLATION
MODES
AND
MITIGATION
OF
VOLTAGE-BASED
ATTACKS
.
162
5.5
INTRA-TILE
MULTICORE
EXTENSION
FOR
THE
Z-CORE
.
164
5.6
NEAR
MEMORY
COMPUTING
EXTENSIONS
.
165
5.6.1
REGION-BASED
NEAR-MEMORY
COMPUTING
.
166
5.6.2
NEAR-MEMORY
COMPUTING
(NMC)
CONTROLLER
.
168
IV
5.6.3
EVALUATION:
AES
ENCRYPTION
PERFORMANCE
.
168
5.7
TASK
SCHEDULING
FOR
RUNTIME-RECONFIGURABLE
PROCESSORS
.
169
5.8
WORST
CASE
EXECUTION
TIME
ANALYSIS
AND
OPTIMISATIONS
FOR
RECON
FIGURABLE
PROCESSORS
.
170
5.9
CONCLUSION
.
173
6
INVASIVE
TIGHTLY-COUPLED
PROCESSOR
ARRAYS
177
JIIRGEN
TEICH,
MARCEL
BRAND,
FRANK
HANNIG,
CHRISTIAN
HEIDORN,
DOMINIK
WALTER,
MICHAEL
WITTERAUF
6.1
INTRODUCTION
.
178
6.2
SAFE(R)
LOOPS
-
FAULT-TOLERANT
PARALLEL
LOOP
PROCESSING
.
180
6.3
ORTHOGONAL
INSTRUCTION
PROCESSING
.
182
6.4
RUN-TIME
REQUIREMENT
ENFORCEMENT
(RRE)
ON
TCPAS
.
183
6.5
ANYTIME
INSTRUCTION
PROCESSORS
(AIP)
.
186
6.5.1
ON-LINE
ARITHMETIC
APPROACH
.
188
6.5.2
BITMASKING
APPROACH
.
189
6.6
REAL-TIME
SCHEDULING
OF
I/O
DATA
TRANSFERS
.
192
6.6.1
GENERATION
OF
DATA
BLOCKS
.
193
6.6.2
REAL-TIME
I/O
SCHEDULING
PROBLEM
.
195
6.6.3
LOOP
I/O
CONTROLLER
.
197
6.6.4
PRIORITY
QUEUE
.
197
6.6.5
CONFIGURATION
UNIT
.
199
6.6.6
DMA
ENGINE
.
199
6.7
CONCLUSIONS
AND
ACKNOWLEDGEMENT
.
200
7
POWER-EFFICIENT
INVASIVE
LOOSELY-COUPLED
MPSOCS
203
JORG
HENKEL,
ANDREAS
HERKERSDORF,
HEBA
KHDR,
MARTIN
RAPP,
MARK
SAGI,
MOHAMMED
BAKR
SIKAL,
THOMAS
WILD
7.1
INTRODUCTION
.
203
7.2
THERMALLY
SAFE
POWER
CONSTRAINTS
.
205
7.3
RULE-BASED
POWER/THERMAL
MANAGEMENT
.
206
7.3.1
CORE
I-LET
CONTROLLER
.
206
7.3.2
THERMAL-CONSTRAINED
APPLICATION
MAPPING
AND
VOLTAGE/
FREQUENCY
(V/F)
SELECTION
.
208
7.4
ML-BASED
POWER/THERMAL
MANAGEMENT
AND
MODELLING
.
209
7.4.1
APPLICATION
MAPPING
AND
V/F
SCALING
.
210
7.4.2
POWER
AND
CACHE-AWARE
APPLICATION
MIGRATION
.
213
7.4.3
APPLICATION-AWARE
BOOSTING
.
216
7.4.4
RUN-TIME
POWER
ESTIMATION
AND
FORECASTING
.
219
7.5
CONCLUSION
.
225
V
8
GENERATION
OF
DISTRIBUTED
MONITORS
AND
RUN-TIME
VERIFICATION
OF
INVASIVE
APPLICATIONS
229
DANIEL
MIILLER-GRITSCHNEDER,
ULF
SCHLICHTMANN,
ALEXANDRA
LISTL,
MARCEL
METTLER,
LI
ZHANG
8.1
INTRODUCTION
.
229
8.2
RUN-TIME
VERIFICATION
OF
INVASIVE
MANY-CORE
SYSTEMS
.
230
8.2.1
SUPPORTED
RUN-TIME
REQUIREMENTS
.
231
8.2.2
ARCHITECTURAL
DESIGN
.
233
8.2.3
BENEFITS
AND
LIMITATIONS
OF
THE
RUN-TIME
VERIFICATION
(RV)
SYSTEM
.
238
8.3
THERMAL
EMULATION
OF
ASICS
ON
FPGA
PROTOTYPES
.
239
8.3.1
ASIC
POWER
EMULATION
.
240
8.3.2
ASIC
TEMPERATURE
EMULATION
.
241
8.3.3
ASIC
DYNAMIC
VOLTAGE
FREQUENCY
SCALING
EMULATION
.
.
.
243
8.4
GENERATION
OF
INVASIVE
APPLICATIONS
.
245
8.5
FPGA-BASED
EVALUATION
OF
STRATEGIES
FOR
THERMAL
AND
RESOURCE
MAN
AGEMENT
.
248
8.6
CONCLUSION
.
251
9
INVASIVE
NOCS
AND
MEMORY
HIERARCHIES
FOR
RUN-TIME
ADAPTIVE
MPSOCS
255
JIIRGEN
BECKER,
ANDREAS
HERKERSDORF,
NIDHI
ANANTHARAJAIAH,
OLIVER
LENKE,
AKSHAY
SRIVATSA,
THOMAS
WILD
9.1
INTRODUCTION
.
255
9.2
INOC
AS
BASIC
INVASIVE
INTERCONNECT
.
257
9.3
ADAPTIVE
MULTI-LAYERED
NOC
AND
DYNAMIC
MULTICAST
SUPPORT
.
.
.
258
9.3.1
MULTI-LAYERED
TOPOLOGIES
.
258
9.3.2
ADAPTIVE
CONGESTION-AWARE
ROUTING
ALGORITHM
.
260
9.3.3
DYNAMIC
BLOCK-BASED
MULTICAST
ROUTING
.
261
9.4
ADAPTIVE
NOC
BASED
ON
ANT
COLONY
OPTIMISATION
.
264
9.4.1
DISTRIBUTED
ROUTING
BASED
ON
ANT
COLONY
OPTIMISATION
.
265
9.5
REGION-BASED
CACHE
COHERENCE
.
268
9.5.1
CONCEPT
.
268
9.5.2
FEATURES
.
268
9.5.3
DESIGN
AND
FUNCTIONALITY
.
270
9.5.4
EVALUATION
.
271
9.6
NEAR-MEMORY
COMPUTING
.
273
9.6.1
CONCEPT
OF
NEAR-MEMORY
GRAPH
COPY
.
275
9.6.2
IMPLEMENTATION
.
276
9.6.3
EVALUATION
.
277
9.7
CONCLUSION
AND
ACKNOWLEDGEMENT
.
279
VI
C:
COMPILER,
SIMULATION
AND
RUN-TIME
SUPPORT
285
10
INVASIVE
RUN-TIME
SUPPORT
SYSTEM
(IRTSS)
285
LARS
BAUER,
JORG
HENKEL,
TIMO
HONIG,
WOLFGANG
SCHRODER-PREIKSCHAT,
CHRISTIAN
EICHLER,
JEFERSON
GONZALEZ,
BENEDICT
HERZOG,
TOBIAS
LANGER,
SEBASTIAN
MAIER,
JONAS
RABENSTEIN,
PHILLIP
RAFFECK,
FLORIAN
SCHMAUS
10.1
INTRODUCTION
.
285
10.2
OCTOPOS
.
286
10.2.1
MEMORY
AND
ADDRESS
SPACES
.
287
10.2.2
PROCESSES
AND
THREADS
.
292
10.2.3
TIME
AND
ENERGY
.
295
10.2.4
EVALUATION
OF
THE
CONCEPTS
.
296
10.3
AGENT
SYSTEM
.
298
10.3.1
EXPRESSING
RESOURCE
REQUIREMENTS
AND
SCALABILITY
BY
CON
STRAINT
SYSTEMS
.
298
10.3.2
DECENTRALISED
AGENT
SYSTEM
(AS)
INFRASTRUCTURE
.
299
10.3.3
RESOURCE
MANAGEMENT
FOR
COMPLEX
CONSTRAINTS
.
300
10.3.4
RESOURCE
MANAGEMENT
FOR
MALLEABLE
APPLICATIONS
.
301
10.3.5
ADAPTIVE
ON-THE-FLY
APPLICATION
PERFORMANCE
MODEL
.
.
.
303
10.3.6
ENFORCING
SECURITY
THROUGH
RESOURCE
MANAGEMENT
.
304
10.4
ACKNOWLEDGEMENT
.
305
11
COMPILATION
AND
CODE
GENERATION
FOR
INVASIVE
PROGRAMS
309
GREGOR
SNELTING,
JIIRGEN
TEICH,
ANDREAS
FRIED,
FRANK
HANNIG,
MICHAEL
WITTERAUF
11.1
INTRODUCTION
.
309
11.2
SYMBOLIC
LOOP
COMPILATION
FOR
TCPAS
.
311
11.2.1
POLYHEDRAL
MODEL
.
313
11.2.2
SYMBOLIC
MAPPING
.
314
11.2.3
INSTANTIATION
.
317
11.2.4
RUN-TIME
REQUIREMENT
ENFORCEMENT
ON
LOOPS
.
319
11.3
COMPILATION
FOR
GENERAL-PURPOSE
CPUS
.
322
11.3.1
INVASIVE
X10
FRONT
END
.
322
11.3.2
PGAS
PROGRAMMING
ON
IRTSS
.
324
11.4
COMPILER
OPTIMISATIONS
.
325
11.4.1
A
NEW
ALGORITHM
FOR
SSA
CONSTRUCTION
.
325
11.4.2
COMPILER
SYNTHESIS
.
325
11.4.3
REGISTER
PERMUTATIONS
.
327
U.4.4
OPTIMISING
INTER-TILE
DATA
TRANSFER
.
328
11.4.5
NEAR-MEMORY
COMPUTING
.
330
11.5
ACKNOWLEDGEMENT
.
331
VII
12
SECURITY
IN
INVASIVE
COMPUTING
SYSTEMS
335
FELIX
FREILING,
WOLFGANG
SCHRODER-PREIKSCHAT,
GREGOR
SNELTING,
INGRID
VERBAUWHEDE,
FRANZISKA
SCHIRRMACHER,
FURKAN
TURAN,
SIMON
BISCHOF
12.1
INTRODUCTION
.
335
12.2
ATTACKER
MODEL
.
336
12.3
SECURITY
REQUIREMENTS
AND
ISOLATION
CONCEPTS
.
337
12.3.1
CONFIDENTIALITY
REQUIREMENTS
.
338
12.3.2
INTEGRITY
REQUIREMENTS
.
339
12.3.3
ISOLATION
CONCEPTS
.
339
12.4
PREVIOUS
WORK
.
340
12.4.1
APPLICATION
AND
SYSTEMS
SOFTWARE
LAYER
.
340
12.4.2
HARDWARE
LAYER
.
342
12.5
INFORMATION
FLOW
CONTROL
VIA
CONTROL
FLOW
ATTESTATION
.
345
12.6
LANGUAGE-BASED
INFORMATION
FLOW
CONTROL
.
347
12.6.1
TIMING-SENSITIVE
INFORMATION
FLOW
CONTROL
.
347
12.6.2
INFORMATION
FLOW
CONTROL
FOR
PARALLEL
PROGRAMS
.
348
12.6.3
QUANTITATIVE
INFORMATION
FLOW
.
349
12.7
RUN-TIME
MONITORING
FOR
SIDE-CHANNEL
DETECTION
.
350
12.8
VIRTUAL
SHARED
MEMORY
ENCRYPTION,
INTEGRITY
AND
ACCESS
.
351
12.9
HARDWARE-BASED
MUTUAL
ATTESTATION
.
352
12.10
SUMMARY
AND
ACKNOWLEDGEMENTS
.
353
D
:
APPLICATIONS
359
13
INVASIVE
SOFTWARE-HARDWARE
ARCHITECTURES
FOR
ROBOTICS
359
TAMIM
ASFOUR,
WALTER
STECHELE,
NAEL
FASFOUS,
FELIX
HUNDHAUSEN,
FABIAN
PAUS
13.1
INTRODUCTION
.
359
13.2
FEATURE
DETECTION
.
360
13.3
OBJECT
CLASSIFICATION
AND
SEGMENTATION
.
362
13.4
LOW-LATENCY
RUN-TIME
ADAPTABLE
BINARY
NEURAL
NETWORK
CLASSIFIER
365
13.5
MOTION
PLANNING
.
370
13.6
EXTRACTING
SUPPORT
RELATIONS
.
374
13.7
ACTION
EFFECT
PREDICTION
.
377
13.8
NETWORK
AND
ROBOT
CO-SIMULATION
.
378
13.9
CONCLUSION
AND
ACKNOWLEDGEMENT
.
379
14
INVASIVE
COMPUTING
AND
HPC
383
MICHAEL
BADER,
HANS-JOACHIM
BUNGARTZ,
MICHAEL
GERNDT,
JOPHIN
JOHN,
SANTIAGO
NARVAEZ
RIVAS,
ISAIAS
A.
COMPRES
URENA
14.1
CHALLENGES
AND
OPPORTUNITIES
.
383
VIII
14.2
INVASIVE
COMPUTING
WITHIN
AN
HPC
NODE
.
386
14.2.1
IOPENMP
CONCEPTS
.
386
14.2.2
IOPENMP
IMPLEMENTATION
.
387
14.2.3
APPLICATIONS
.
388
14.3
INVASIVE
COMPUTING
FOR
LARGE
SCALE
HPC
SYSTEMS
.
389
14.3.1
IMPI
CONCEPTS
.
389
14.3.2
IMPI
IMPLEMENTATION
.
390
14.3.3
APPLICATIONS
.
392
14.3.4
ELASTIC-PHASE
ORIENTED
PROGRAMMING
MODEL
.
394
14.4
DATA
CENTRE
LEVEL
INVASIVE
SERVICES
.
396
14.4.1
ENABLING
INTERACTIVE
WORKLOADS
.
396
14.4.2
POWER
CORRIDOR
MANAGEMENT
.
398
14.4.3
INVASIVE
CHECKPOINTING
.
401
14.5
INTEGRATING
IMPI
WITH
THE
X86
NATIVE
OCTOPOS
PLATFORM
.
405
14.5.1
APPROACH
.
405
14.5.2
IMPLEMENTATION
.
406
14.5.3
APPLICATIONS
.
406
14.6
SUMMARY
AND
OUTLOOK
.
408
5
VALIDATION
AND
DEMONSTRATOR
411
JIIRGEN
BECKER,
FRANK
HANNIG,
THOMAS
WILD,
MARCEL
BRAND,
OLIVER
LENKE,
FABIAN
LESNIAK
15.1
INTRODUCTION
.
411
15.2
FPGA
PROTOTYPING
PLATFORM
.
413
15.2.1
INTER-FPGA
PIN
MULTIPLEXING
.
413
15.2.2
MEMORY
AND
INTERFACING
.
414
15.2.3
CONFIGURATION
AND
DEBUGGING
.
415
15.3
INVASIVE
ARCHITECTURE
PROTOTYPE
.
415
15.3.1
INVASIVE
NETWORK-ON-CHIP
.
.
417
15.3.2
PROCESSOR
TILES
.
417
15.3.3
Z-CORE
TILES
.
420
15.3.4
TCPA
TILES
.
420
15.3.5
SHARED
MEMORY
TILE
.
421
15.3.6
I/O
TILES
.
421
15.3.7
ADDRESS
MAPPING
.
421
15.3.8
NON-INTRUSIVE
MONITORING
SYSTEM
.
422
15.4
INTEGRATION
PROCEDURE
AND
DEBUGGING
.
423
15.5
INVASIVE
COMPUTING
DEMONSTRATORS
.
424
15.5.1
ENFORCEMENT
DEMONSTRATOR
.
425
15.5.2
PROSTHETIC HAND
DEMONSTRATOR
.
429
15.6
CONCLUSION
AND
ACKNOWLEDGEMENT
.
430
IX |
| adam_txt |
CONTENTS
I
INTRODUCTION
TO
INVASIVE
COMPUTING
I
JIIRGEN
TEICH,
JORG
HENKEL,
ANDREAS
HERKERSDORF
1.1
WHAT
IS
INVASIVE
COMPUTING?
.
2
1.2
LONG-TERM
RESEARCH
GOALS
AND
VISION
.
6
1.3
ACHIEVEMENTS
IN
FIRST
AND
SECOND
FUNDING
PHASES
(2010-2018)
.
.
13
1.4
ASSESSMENT
OF
PROJECT
STRUCTURE
.
41
1.5
RESEARCH
FOCUS
IN
THE
THIRD
FUNDING
PHASE
(2018-2022)
.
43
1.5.1
GOALS
AND
STRATEGY
.
43
1.5.2
RESEARCH
FOCUS
PER
PROJECT
AREA
.
44
1.5.3
INVASIC
VALIDATION
AND
DEMONSTRATOR
ROAD
MAP
.
53
1.5.4
WORKING
GROUPS
-
DEVELOPING
CROSS-PROJECT
SYNERGIES
.
.
55
A:
FUNDAMENTALS,
LANGUAGE
AND
ALGORITHM
RESEARCH
69
2
BASICS
OF
INVASIVE
COMPUTING
69
JIIRGEN
TEICH,
KHALIL
ESPER,
JOACHIM
FALK,
BEHNAZ
POURMOHSENI,
TOBIAS
SCHWARZER,
STEFAN
WILDERMANN
2.1
RUN-TIME
REQUIREMENT
ENFORCEMENT
(RRE)
.
69
2.2
TAXONOMY
OF
RUN-TIME
REQUIREMENT
ENFORCERS
.
71
2.3
APPLICATION
CHARACTERISATION
AND
ENFORCEMENT
ACTIONS
.
73
2.4
POWER,
LATENCY,
AND
ENERGY
MODEL
.
74
2.5
ENERGY-MINIMISED
TIMING
ENFORCEMENT
.
77
2.6
DISTRIBUTED
ENFORCEMENT
.
78
2.7
FEEDBACK-BASED
ENFORCEMENT
STRATEGIES
.
81
2.7.1
FORMAL
DEFINITIONS
.
82
2.7.2
VERIFICATION
GOALS
.
85
2.7.3
PROPERTY
SPECIFICATION
IN
PRISM
.
87
2.7.4
VERIFICATION
RESULTS
.
88
2.8
CONCLUSIONS
AND
ACKNOWLEDGEMENT
.
92
3
CHARACTERISATION
AND
ANALYSIS
OF
INVASIVE
ALGORITHMIC
PATTERNS
97
MICHAEL
BADER,
STEFAN
WILDERMANN,
MICHAEL
GLAFI,
ALEXANDER
POPPI,
BEHNAZ
POURMOHSENI,
TOBIAS
SCHWARZER,
JAN
SPIECK,
MARIO
WILLE
3.1
INTRODUCTION
.
97
3.2
ALGORITHMIC
PATTERNS
.
98
3.2.1
THE
SHALLOW
WATER
EQUATIONS
.
98
3.2.2
SWE-X10
.
100
III
3.3
HYBRID
APPLICATION
MAPPING
.
105
3.3.1
COMPLEXITY
REDUCTION
.
107
3.3.2
COMPOSABILITY
.
108
3.3.3
MAPPING
RECONFIGURATION
AND
TASK
MIGRATION
.
109
3.3.4
SCENARIO-AWARE
HAM
.
109
3.4
CONCLUSIONS
AND
ACKNOWLEDGEMENTS
.
119
4
SCHEDULING
INVASIVE
MULTICORE
PROGRAMS
UNDER
UNCERTAINTY
123
NICOLE
MEGOW,
ALEXANDER
LINDERMAYR,
BERTRAND
SIMON
4.1
INTRODUCTION
.
123
4.2
UNCERTAIN
EXECUTION
TIMES
.
124
4.2.1
LEARNING-AUGMENTED
ALGORITHM
DESIGN
.
125
4.2.2
PREDICTION
MODEL
AND
ERROR
DEFINITION
.
127
4.2.3
THE
PREFERENTIAL
TIME
SHARING
FRAMEWORK
.
129
4.2.4
EXPERIMENTAL
EVALUATION
.
131
4.3
UNCERTAIN
TASK
GRAPHS
.
135
4.4
UNCERTAIN
PROCESSOR
AVAILABILITY
OR
SPEED
.
139
4.5
SPEED-SCALING
FOR
RUN-TIME
REQUIREMENT
ENFORCEMENT
AND
POWER
MANAGEMENT
.
142
4.6
CONCLUSION
.
145
B:
ARCHITECTURAL
RESEARCH
151
5
ADAPTIVE
APPLICATION-SPECIFIC
INVASIVE
MICRO-ARCHITECTURES
151
LARS
BAUER,
JIIRGEN
BECKER,
JORG
HENKEL,
FABIAN
LESNIAK,
HASSAN
NASSAR
5.1
INTRODUCTION
.
151
5.1.1
OVERVIEW
OF
THE
Z-CORE
ARCHITECTURE
.
152
5.1.2
PROTOTYPE
AND
INTEGRATION
.
154
5.2
GENERATING
AND
USING
SPECIAL
INSTRUCTIONS
(SIS)
.
154
5.2.1
EXAMPLES
FOR
SIS
AND
ACCELERATORS
.
155
5.2.2
AUTOMATIC
GENERATION
OF
SIS
DURING
RUNTIME
.
157
5.3
RUN-TIME
ADAPTIVE
CACHE
ARCHITECTURES
.
158
5.3.1
INTRA-TILE
CACHE
RE-ALLOCATION
.
158
5.3.2
ASSOCIATIVITY
AND
CACHE
SIZE
IMPACT
.
159
5.4
SECURITY
ASPECTS
OF
THE
Z-CORE
.
161
5.4.1
INFORMATION
LEAKAGE
PROTECTION
.
161
5.4.2
ISOLATION
MODES
AND
MITIGATION
OF
VOLTAGE-BASED
ATTACKS
.
162
5.5
INTRA-TILE
MULTICORE
EXTENSION
FOR
THE
Z-CORE
.
164
5.6
NEAR
MEMORY
COMPUTING
EXTENSIONS
.
165
5.6.1
REGION-BASED
NEAR-MEMORY
COMPUTING
.
166
5.6.2
NEAR-MEMORY
COMPUTING
(NMC)
CONTROLLER
.
168
IV
5.6.3
EVALUATION:
AES
ENCRYPTION
PERFORMANCE
.
168
5.7
TASK
SCHEDULING
FOR
RUNTIME-RECONFIGURABLE
PROCESSORS
.
169
5.8
WORST
CASE
EXECUTION
TIME
ANALYSIS
AND
OPTIMISATIONS
FOR
RECON
FIGURABLE
PROCESSORS
.
170
5.9
CONCLUSION
.
173
6
INVASIVE
TIGHTLY-COUPLED
PROCESSOR
ARRAYS
177
JIIRGEN
TEICH,
MARCEL
BRAND,
FRANK
HANNIG,
CHRISTIAN
HEIDORN,
DOMINIK
WALTER,
MICHAEL
WITTERAUF
6.1
INTRODUCTION
.
178
6.2
SAFE(R)
LOOPS
-
FAULT-TOLERANT
PARALLEL
LOOP
PROCESSING
.
180
6.3
ORTHOGONAL
INSTRUCTION
PROCESSING
.
182
6.4
RUN-TIME
REQUIREMENT
ENFORCEMENT
(RRE)
ON
TCPAS
.
183
6.5
ANYTIME
INSTRUCTION
PROCESSORS
(AIP)
.
186
6.5.1
ON-LINE
ARITHMETIC
APPROACH
.
188
6.5.2
BITMASKING
APPROACH
.
189
6.6
REAL-TIME
SCHEDULING
OF
I/O
DATA
TRANSFERS
.
192
6.6.1
GENERATION
OF
DATA
BLOCKS
.
193
6.6.2
REAL-TIME
I/O
SCHEDULING
PROBLEM
.
195
6.6.3
LOOP
I/O
CONTROLLER
.
197
6.6.4
PRIORITY
QUEUE
.
197
6.6.5
CONFIGURATION
UNIT
.
199
6.6.6
DMA
ENGINE
.
199
6.7
CONCLUSIONS
AND
ACKNOWLEDGEMENT
.
200
7
POWER-EFFICIENT
INVASIVE
LOOSELY-COUPLED
MPSOCS
203
JORG
HENKEL,
ANDREAS
HERKERSDORF,
HEBA
KHDR,
MARTIN
RAPP,
MARK
SAGI,
MOHAMMED
BAKR
SIKAL,
THOMAS
WILD
7.1
INTRODUCTION
.
203
7.2
THERMALLY
SAFE
POWER
CONSTRAINTS
.
205
7.3
RULE-BASED
POWER/THERMAL
MANAGEMENT
.
206
7.3.1
CORE
I-LET
CONTROLLER
.
206
7.3.2
THERMAL-CONSTRAINED
APPLICATION
MAPPING
AND
VOLTAGE/
FREQUENCY
(V/F)
SELECTION
.
208
7.4
ML-BASED
POWER/THERMAL
MANAGEMENT
AND
MODELLING
.
209
7.4.1
APPLICATION
MAPPING
AND
V/F
SCALING
.
210
7.4.2
POWER
AND
CACHE-AWARE
APPLICATION
MIGRATION
.
213
7.4.3
APPLICATION-AWARE
BOOSTING
.
216
7.4.4
RUN-TIME
POWER
ESTIMATION
AND
FORECASTING
.
219
7.5
CONCLUSION
.
225
V
8
GENERATION
OF
DISTRIBUTED
MONITORS
AND
RUN-TIME
VERIFICATION
OF
INVASIVE
APPLICATIONS
229
DANIEL
MIILLER-GRITSCHNEDER,
ULF
SCHLICHTMANN,
ALEXANDRA
LISTL,
MARCEL
METTLER,
LI
ZHANG
8.1
INTRODUCTION
.
229
8.2
RUN-TIME
VERIFICATION
OF
INVASIVE
MANY-CORE
SYSTEMS
.
230
8.2.1
SUPPORTED
RUN-TIME
REQUIREMENTS
.
231
8.2.2
ARCHITECTURAL
DESIGN
.
233
8.2.3
BENEFITS
AND
LIMITATIONS
OF
THE
RUN-TIME
VERIFICATION
(RV)
SYSTEM
.
238
8.3
THERMAL
EMULATION
OF
ASICS
ON
FPGA
PROTOTYPES
.
239
8.3.1
ASIC
POWER
EMULATION
.
240
8.3.2
ASIC
TEMPERATURE
EMULATION
.
241
8.3.3
ASIC
DYNAMIC
VOLTAGE
FREQUENCY
SCALING
EMULATION
.
.
.
243
8.4
GENERATION
OF
INVASIVE
APPLICATIONS
.
245
8.5
FPGA-BASED
EVALUATION
OF
STRATEGIES
FOR
THERMAL
AND
RESOURCE
MAN
AGEMENT
.
248
8.6
CONCLUSION
.
251
9
INVASIVE
NOCS
AND
MEMORY
HIERARCHIES
FOR
RUN-TIME
ADAPTIVE
MPSOCS
255
JIIRGEN
BECKER,
ANDREAS
HERKERSDORF,
NIDHI
ANANTHARAJAIAH,
OLIVER
LENKE,
AKSHAY
SRIVATSA,
THOMAS
WILD
9.1
INTRODUCTION
.
255
9.2
INOC
AS
BASIC
INVASIVE
INTERCONNECT
.
257
9.3
ADAPTIVE
MULTI-LAYERED
NOC
AND
DYNAMIC
MULTICAST
SUPPORT
.
.
.
258
9.3.1
MULTI-LAYERED
TOPOLOGIES
.
258
9.3.2
ADAPTIVE
CONGESTION-AWARE
ROUTING
ALGORITHM
.
260
9.3.3
DYNAMIC
BLOCK-BASED
MULTICAST
ROUTING
.
261
9.4
ADAPTIVE
NOC
BASED
ON
ANT
COLONY
OPTIMISATION
.
264
9.4.1
DISTRIBUTED
ROUTING
BASED
ON
ANT
COLONY
OPTIMISATION
.
265
9.5
REGION-BASED
CACHE
COHERENCE
.
268
9.5.1
CONCEPT
.
268
9.5.2
FEATURES
.
268
9.5.3
DESIGN
AND
FUNCTIONALITY
.
270
9.5.4
EVALUATION
.
271
9.6
NEAR-MEMORY
COMPUTING
.
273
9.6.1
CONCEPT
OF
NEAR-MEMORY
GRAPH
COPY
.
275
9.6.2
IMPLEMENTATION
.
276
9.6.3
EVALUATION
.
277
9.7
CONCLUSION
AND
ACKNOWLEDGEMENT
.
279
VI
C:
COMPILER,
SIMULATION
AND
RUN-TIME
SUPPORT
285
10
INVASIVE
RUN-TIME
SUPPORT
SYSTEM
(IRTSS)
285
LARS
BAUER,
JORG
HENKEL,
TIMO
HONIG,
WOLFGANG
SCHRODER-PREIKSCHAT,
CHRISTIAN
EICHLER,
JEFERSON
GONZALEZ,
BENEDICT
HERZOG,
TOBIAS
LANGER,
SEBASTIAN
MAIER,
JONAS
RABENSTEIN,
PHILLIP
RAFFECK,
FLORIAN
SCHMAUS
10.1
INTRODUCTION
.
285
10.2
OCTOPOS
.
286
10.2.1
MEMORY
AND
ADDRESS
SPACES
.
287
10.2.2
PROCESSES
AND
THREADS
.
292
10.2.3
TIME
AND
ENERGY
.
295
10.2.4
EVALUATION
OF
THE
CONCEPTS
.
296
10.3
AGENT
SYSTEM
.
298
10.3.1
EXPRESSING
RESOURCE
REQUIREMENTS
AND
SCALABILITY
BY
CON
STRAINT
SYSTEMS
.
298
10.3.2
DECENTRALISED
AGENT
SYSTEM
(AS)
INFRASTRUCTURE
.
299
10.3.3
RESOURCE
MANAGEMENT
FOR
COMPLEX
CONSTRAINTS
.
300
10.3.4
RESOURCE
MANAGEMENT
FOR
MALLEABLE
APPLICATIONS
.
301
10.3.5
ADAPTIVE
ON-THE-FLY
APPLICATION
PERFORMANCE
MODEL
.
.
.
303
10.3.6
ENFORCING
SECURITY
THROUGH
RESOURCE
MANAGEMENT
.
304
10.4
ACKNOWLEDGEMENT
.
305
11
COMPILATION
AND
CODE
GENERATION
FOR
INVASIVE
PROGRAMS
309
GREGOR
SNELTING,
JIIRGEN
TEICH,
ANDREAS
FRIED,
FRANK
HANNIG,
MICHAEL
WITTERAUF
11.1
INTRODUCTION
.
309
11.2
SYMBOLIC
LOOP
COMPILATION
FOR
TCPAS
.
311
11.2.1
POLYHEDRAL
MODEL
.
313
11.2.2
SYMBOLIC
MAPPING
.
314
11.2.3
INSTANTIATION
.
317
11.2.4
RUN-TIME
REQUIREMENT
ENFORCEMENT
ON
LOOPS
.
319
11.3
COMPILATION
FOR
GENERAL-PURPOSE
CPUS
.
322
11.3.1
INVASIVE
X10
FRONT
END
.
322
11.3.2
PGAS
PROGRAMMING
ON
IRTSS
.
324
11.4
COMPILER
OPTIMISATIONS
.
325
11.4.1
A
NEW
ALGORITHM
FOR
SSA
CONSTRUCTION
.
325
11.4.2
COMPILER
SYNTHESIS
.
325
11.4.3
REGISTER
PERMUTATIONS
.
327
U.4.4
OPTIMISING
INTER-TILE
DATA
TRANSFER
.
328
11.4.5
NEAR-MEMORY
COMPUTING
.
330
11.5
ACKNOWLEDGEMENT
.
331
VII
12
SECURITY
IN
INVASIVE
COMPUTING
SYSTEMS
335
FELIX
FREILING,
WOLFGANG
SCHRODER-PREIKSCHAT,
GREGOR
SNELTING,
INGRID
VERBAUWHEDE,
FRANZISKA
SCHIRRMACHER,
FURKAN
TURAN,
SIMON
BISCHOF
12.1
INTRODUCTION
.
335
12.2
ATTACKER
MODEL
.
336
12.3
SECURITY
REQUIREMENTS
AND
ISOLATION
CONCEPTS
.
337
12.3.1
CONFIDENTIALITY
REQUIREMENTS
.
338
12.3.2
INTEGRITY
REQUIREMENTS
.
339
12.3.3
ISOLATION
CONCEPTS
.
339
12.4
PREVIOUS
WORK
.
340
12.4.1
APPLICATION
AND
SYSTEMS
SOFTWARE
LAYER
.
340
12.4.2
HARDWARE
LAYER
.
342
12.5
INFORMATION
FLOW
CONTROL
VIA
CONTROL
FLOW
ATTESTATION
.
345
12.6
LANGUAGE-BASED
INFORMATION
FLOW
CONTROL
.
347
12.6.1
TIMING-SENSITIVE
INFORMATION
FLOW
CONTROL
.
347
12.6.2
INFORMATION
FLOW
CONTROL
FOR
PARALLEL
PROGRAMS
.
348
12.6.3
QUANTITATIVE
INFORMATION
FLOW
.
349
12.7
RUN-TIME
MONITORING
FOR
SIDE-CHANNEL
DETECTION
.
350
12.8
VIRTUAL
SHARED
MEMORY
ENCRYPTION,
INTEGRITY
AND
ACCESS
.
351
12.9
HARDWARE-BASED
MUTUAL
ATTESTATION
.
352
12.10
SUMMARY
AND
ACKNOWLEDGEMENTS
.
353
D
:
APPLICATIONS
359
13
INVASIVE
SOFTWARE-HARDWARE
ARCHITECTURES
FOR
ROBOTICS
359
TAMIM
ASFOUR,
WALTER
STECHELE,
NAEL
FASFOUS,
FELIX
HUNDHAUSEN,
FABIAN
PAUS
13.1
INTRODUCTION
.
359
13.2
FEATURE
DETECTION
.
360
13.3
OBJECT
CLASSIFICATION
AND
SEGMENTATION
.
362
13.4
LOW-LATENCY
RUN-TIME
ADAPTABLE
BINARY
NEURAL
NETWORK
CLASSIFIER
365
13.5
MOTION
PLANNING
.
370
13.6
EXTRACTING
SUPPORT
RELATIONS
.
374
13.7
ACTION
EFFECT
PREDICTION
.
377
13.8
NETWORK
AND
ROBOT
CO-SIMULATION
.
378
13.9
CONCLUSION
AND
ACKNOWLEDGEMENT
.
379
14
INVASIVE
COMPUTING
AND
HPC
383
MICHAEL
BADER,
HANS-JOACHIM
BUNGARTZ,
MICHAEL
GERNDT,
JOPHIN
JOHN,
SANTIAGO
NARVAEZ
RIVAS,
ISAIAS
A.
COMPRES
URENA
14.1
CHALLENGES
AND
OPPORTUNITIES
.
383
VIII
14.2
INVASIVE
COMPUTING
WITHIN
AN
HPC
NODE
.
386
14.2.1
IOPENMP
CONCEPTS
.
386
14.2.2
IOPENMP
IMPLEMENTATION
.
387
14.2.3
APPLICATIONS
.
388
14.3
INVASIVE
COMPUTING
FOR
LARGE
SCALE
HPC
SYSTEMS
.
389
14.3.1
IMPI
CONCEPTS
.
389
14.3.2
IMPI
IMPLEMENTATION
.
390
14.3.3
APPLICATIONS
.
392
14.3.4
ELASTIC-PHASE
ORIENTED
PROGRAMMING
MODEL
.
394
14.4
DATA
CENTRE
LEVEL
INVASIVE
SERVICES
.
396
14.4.1
ENABLING
INTERACTIVE
WORKLOADS
.
396
14.4.2
POWER
CORRIDOR
MANAGEMENT
.
398
14.4.3
INVASIVE
CHECKPOINTING
.
401
14.5
INTEGRATING
IMPI
WITH
THE
X86
NATIVE
OCTOPOS
PLATFORM
.
405
14.5.1
APPROACH
.
405
14.5.2
IMPLEMENTATION
.
406
14.5.3
APPLICATIONS
.
406
14.6
SUMMARY
AND
OUTLOOK
.
408
5
VALIDATION
AND
DEMONSTRATOR
411
JIIRGEN
BECKER,
FRANK
HANNIG,
THOMAS
WILD,
MARCEL
BRAND,
OLIVER
LENKE,
FABIAN
LESNIAK
15.1
INTRODUCTION
.
411
15.2
FPGA
PROTOTYPING
PLATFORM
.
413
15.2.1
INTER-FPGA
PIN
MULTIPLEXING
.
413
15.2.2
MEMORY
AND
INTERFACING
.
414
15.2.3
CONFIGURATION
AND
DEBUGGING
.
415
15.3
INVASIVE
ARCHITECTURE
PROTOTYPE
.
415
15.3.1
INVASIVE
NETWORK-ON-CHIP
.
.
417
15.3.2
PROCESSOR
TILES
.
417
15.3.3
Z-CORE
TILES
.
420
15.3.4
TCPA
TILES
.
420
15.3.5
SHARED
MEMORY
TILE
.
421
15.3.6
I/O
TILES
.
421
15.3.7
ADDRESS
MAPPING
.
421
15.3.8
NON-INTRUSIVE
MONITORING
SYSTEM
.
422
15.4
INTEGRATION
PROCEDURE
AND
DEBUGGING
.
423
15.5
INVASIVE
COMPUTING
DEMONSTRATORS
.
424
15.5.1
ENFORCEMENT
DEMONSTRATOR
.
425
15.5.2
PROSTHETIC HAND
DEMONSTRATOR
.
429
15.6
CONCLUSION
AND
ACKNOWLEDGEMENT
.
430
IX |
| any_adam_object | 1 |
| any_adam_object_boolean | 1 |
| author2 | Teich, Jürgen 1964- |
| author2_role | edt |
| author2_variant | j t jt |
| author_GND | (DE-588)113591942 |
| author_facet | Teich, Jürgen 1964- |
| building | Verbundindex |
| bvnumber | BV048451107 |
| collection | ebook |
| ctrlnum | (OCoLC)1343010421 (DE-599)DNB1266112472 |
| doi_str_mv | 10.25593/978-3-96147-571-1 |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00000nam a22000008c 4500</leader><controlfield tag="001">BV048451107</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20241025</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">220901s2022 gw a||| |||| 00||| eng d</controlfield><datafield tag="015" ind1=" " ind2=" "><subfield code="a">22,N35</subfield><subfield code="2">dnb</subfield></datafield><datafield tag="016" ind1="7" ind2=" "><subfield code="a">1266112472</subfield><subfield code="2">DE-101</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9783961475704</subfield><subfield code="c">Broschur: EUR 54.50 (DE), EUR 56.10 (AT)</subfield><subfield code="9">978-3-96147-570-4</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">3961475709</subfield><subfield code="9">3-96147-570-9</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9783961475711</subfield><subfield code="c">OnlineAusgabe</subfield><subfield code="9">978-3-96147-571-1</subfield></datafield><datafield tag="024" ind1="3" ind2=" "><subfield code="a">9783961475704</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1343010421</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)DNB1266112472</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">gw</subfield><subfield code="c">XA-DE-BY</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-29</subfield><subfield code="a">DE-12</subfield><subfield code="a">DE-29T</subfield><subfield code="a">DE-860</subfield><subfield code="a">DE-91</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="8">1\p</subfield><subfield code="a">004</subfield><subfield code="2">23sdnb</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Invasive computing</subfield><subfield code="c">Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Eds.)</subfield></datafield><datafield tag="246" ind1="1" ind2="3"><subfield code="a">Invasives Rechnen</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Erlangen</subfield><subfield code="b">FAU University Press</subfield><subfield code="c">2022</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">ix, 431 Seiten</subfield><subfield code="b">Illustrationen, Diagramme</subfield><subfield code="c">24 cm x 17 cm, 1067 g</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Datenverarbeitungssystem</subfield><subfield code="0">(DE-588)4125229-9</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Parallelverarbeitung</subfield><subfield code="0">(DE-588)4075860-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Programmierung</subfield><subfield code="0">(DE-588)4076370-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Parallelprogrammierung</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Dienstgüte</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Network-on-Chip</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Chip-Multiprozessor</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">System-on-Chip</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Parallelverarbeitung</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Ressourcenverwaltung</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Hardwarebeschleunigung</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Ablaufplanung</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Parallel Computing</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Multicore Computer Architecture</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Resource-aware Programming</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Run-time Systems</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Compilation</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Datenverarbeitungssystem</subfield><subfield code="0">(DE-588)4125229-9</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Parallelverarbeitung</subfield><subfield code="0">(DE-588)4075860-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">Programmierung</subfield><subfield code="0">(DE-588)4076370-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Teich, Jürgen</subfield><subfield code="d">1964-</subfield><subfield code="0">(DE-588)113591942</subfield><subfield code="4">edt</subfield></datafield><datafield tag="710" ind1="2" ind2=" "><subfield code="a">FAU University Press ein Imprint der Universität Erlangen-Nürnberg</subfield><subfield code="b">Universitätsbibliothek</subfield><subfield code="0">(DE-588)1068111240</subfield><subfield code="4">pbl</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Online-Ausgabe</subfield><subfield code="t">Invasive Computing</subfield><subfield code="d">Erlangen : FAU University Press, 2022</subfield><subfield code="h">Online-Ressource</subfield><subfield code="z">978-3-96147-571-1</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Online-Ausgabe</subfield><subfield code="o">10.25593/978-3-96147-571-1</subfield><subfield code="o">urn:nbn:de:bvb:29-opus4-200331</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">https://open.fau.de/handle/openfau/20033</subfield><subfield code="x">Verlag</subfield><subfield code="z">kostenfrei</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">https://doi.org/10.25593/978-3-96147-571-1</subfield><subfield code="x">Resolving-System</subfield><subfield code="z">kostenfrei</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-200331</subfield><subfield code="x">Resolving-System</subfield><subfield code="z">kostenfrei</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">https://d-nb.info/1266414916/34</subfield><subfield code="x">Langzeitarchivierung Nationalbibliothek</subfield><subfield code="z">kostenfrei</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">DNB Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=033829258&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">vlb</subfield><subfield code="d">20220823</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#vlb</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ebook</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-033829258</subfield></datafield></record></collection> |
| id | DE-604.BV048451107 |
| illustrated | Illustrated |
| index_date | 2024-07-03T20:30:44Z |
| indexdate | 2024-10-25T12:01:29Z |
| institution | BVB |
| institution_GND | (DE-588)1068111240 |
| isbn | 9783961475704 3961475709 9783961475711 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-033829258 |
| oclc_num | 1343010421 |
| open_access_boolean | 1 |
| owner | DE-29 DE-12 DE-29T DE-860 DE-91 DE-BY-TUM |
| owner_facet | DE-29 DE-12 DE-29T DE-860 DE-91 DE-BY-TUM |
| physical | ix, 431 Seiten Illustrationen, Diagramme 24 cm x 17 cm, 1067 g |
| psigel | ebook |
| publishDate | 2022 |
| publishDateSearch | 2022 |
| publishDateSort | 2022 |
| publisher | FAU University Press |
| record_format | marc |
| spelling | Invasive computing Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Eds.) Invasives Rechnen Erlangen FAU University Press 2022 ix, 431 Seiten Illustrationen, Diagramme 24 cm x 17 cm, 1067 g txt rdacontent n rdamedia nc rdacarrier Datenverarbeitungssystem (DE-588)4125229-9 gnd rswk-swf Parallelverarbeitung (DE-588)4075860-6 gnd rswk-swf Programmierung (DE-588)4076370-5 gnd rswk-swf Parallelprogrammierung Dienstgüte Network-on-Chip Chip-Multiprozessor System-on-Chip Parallelverarbeitung Ressourcenverwaltung Hardwarebeschleunigung Ablaufplanung Parallel Computing Multicore Computer Architecture Resource-aware Programming Run-time Systems Compilation Datenverarbeitungssystem (DE-588)4125229-9 s Parallelverarbeitung (DE-588)4075860-6 s Programmierung (DE-588)4076370-5 s DE-604 Teich, Jürgen 1964- (DE-588)113591942 edt FAU University Press ein Imprint der Universität Erlangen-Nürnberg Universitätsbibliothek (DE-588)1068111240 pbl Erscheint auch als Online-Ausgabe Invasive Computing Erlangen : FAU University Press, 2022 Online-Ressource 978-3-96147-571-1 Erscheint auch als Online-Ausgabe 10.25593/978-3-96147-571-1 urn:nbn:de:bvb:29-opus4-200331 https://open.fau.de/handle/openfau/20033 Verlag kostenfrei Volltext https://doi.org/10.25593/978-3-96147-571-1 Resolving-System kostenfrei Volltext https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-200331 Resolving-System kostenfrei Volltext https://d-nb.info/1266414916/34 Langzeitarchivierung Nationalbibliothek kostenfrei Volltext DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=033829258&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p vlb 20220823 DE-101 https://d-nb.info/provenance/plan#vlb |
| spellingShingle | Invasive computing Datenverarbeitungssystem (DE-588)4125229-9 gnd Parallelverarbeitung (DE-588)4075860-6 gnd Programmierung (DE-588)4076370-5 gnd |
| subject_GND | (DE-588)4125229-9 (DE-588)4075860-6 (DE-588)4076370-5 |
| title | Invasive computing |
| title_alt | Invasives Rechnen |
| title_auth | Invasive computing |
| title_exact_search | Invasive computing |
| title_exact_search_txtP | Invasive computing |
| title_full | Invasive computing Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Eds.) |
| title_fullStr | Invasive computing Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Eds.) |
| title_full_unstemmed | Invasive computing Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Eds.) |
| title_short | Invasive computing |
| title_sort | invasive computing |
| topic | Datenverarbeitungssystem (DE-588)4125229-9 gnd Parallelverarbeitung (DE-588)4075860-6 gnd Programmierung (DE-588)4076370-5 gnd |
| topic_facet | Datenverarbeitungssystem Parallelverarbeitung Programmierung |
| url | https://open.fau.de/handle/openfau/20033 https://doi.org/10.25593/978-3-96147-571-1 https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-200331 https://d-nb.info/1266414916/34 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=033829258&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT teichjurgen invasivecomputing AT fauuniversitypresseinimprintderuniversitaterlangennurnberguniversitatsbibliothek invasivecomputing AT teichjurgen invasivesrechnen AT fauuniversitypresseinimprintderuniversitaterlangennurnberguniversitatsbibliothek invasivesrechnen |