Digital VLSI design and simulation with Verilog:
Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Newark
John Wiley & Sons, Incorporated
2021
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| Subjects: | |
| Item Description: | Description based on publisher supplied metadata and other sources |
| Physical Description: | 1 Online-Ressource (222 Seiten) |
| ISBN: | 9781119778097 9781119778066 |
Staff View
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Record in the Search Index
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| author | Lata Tripathi, Suman Saxena, Sobhit Sinha, Sanjeet K. Patel, Govind S. |
| author_facet | Lata Tripathi, Suman Saxena, Sobhit Sinha, Sanjeet K. Patel, Govind S. |
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| author_sort | Lata Tripathi, Suman |
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | DE-604.BV048221462 |
| illustrated | Not Illustrated |
| index_date | 2024-07-03T19:50:32Z |
| indexdate | 2024-07-10T09:32:25Z |
| institution | BVB |
| isbn | 9781119778097 9781119778066 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-033602199 |
| oclc_num | 1289368913 |
| open_access_boolean | |
| owner | DE-83 |
| owner_facet | DE-83 |
| physical | 1 Online-Ressource (222 Seiten) |
| psigel | ZDB-35-WIC ZDB-30-PQE TUM_PDA_PQE |
| publishDate | 2021 |
| publishDateSearch | 2021 |
| publishDateSort | 2021 |
| publisher | John Wiley & Sons, Incorporated |
| record_format | marc |
| spelling | Lata Tripathi, Suman Verfasser aut Digital VLSI design and simulation with Verilog Newark John Wiley & Sons, Incorporated 2021 ©2022 1 Online-Ressource (222 Seiten) txt rdacontent c rdamedia cr rdacarrier Description based on publisher supplied metadata and other sources VERILOG (DE-588)4268385-3 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf VLSI (DE-588)4117388-0 s VERILOG (DE-588)4268385-3 s DE-604 Saxena, Sobhit Verfasser aut Sinha, Sanjeet K. Verfasser aut Patel, Govind S. Verfasser aut Erscheint auch als Druck-Ausgabe 978-1-119-77804-2 |
| spellingShingle | Lata Tripathi, Suman Saxena, Sobhit Sinha, Sanjeet K. Patel, Govind S. Digital VLSI design and simulation with Verilog VERILOG (DE-588)4268385-3 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4268385-3 (DE-588)4117388-0 |
| title | Digital VLSI design and simulation with Verilog |
| title_auth | Digital VLSI design and simulation with Verilog |
| title_exact_search | Digital VLSI design and simulation with Verilog |
| title_exact_search_txtP | Digital VLSI design and simulation with Verilog |
| title_full | Digital VLSI design and simulation with Verilog |
| title_fullStr | Digital VLSI design and simulation with Verilog |
| title_full_unstemmed | Digital VLSI design and simulation with Verilog |
| title_short | Digital VLSI design and simulation with Verilog |
| title_sort | digital vlsi design and simulation with verilog |
| topic | VERILOG (DE-588)4268385-3 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | VERILOG VLSI |
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