APA (7th ed.) Citation

Lata Tripathi, S., Saxena, S., Sinha, S. K., & Patel, G. S. (2021). Digital VLSI design and simulation with Verilog. John Wiley & Sons, Incorporated.

Chicago Style (17th ed.) Citation

Lata Tripathi, Suman, Sobhit Saxena, Sanjeet K. Sinha, and Govind S. Patel. Digital VLSI Design and Simulation with Verilog. Newark: John Wiley & Sons, Incorporated, 2021.

MLA (9th ed.) Citation

Lata Tripathi, Suman, et al. Digital VLSI Design and Simulation with Verilog. John Wiley & Sons, Incorporated, 2021.