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| 245 | 1 | 0 | |a Digital VLSI Design and Simulation with Verilog |c Dr. Suman Lata Tripathi, Dr. Sobhit Saxena, Dr. Sanjeet Kumar Sinha, Dr. Govind Singh Patel |
| 250 | |a 1st edition | ||
| 264 | 1 | |a Hoboken |b Wiley |c 2022 | |
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| 700 | 1 | |a Saxena, Sobhit |e Verfasser |4 aut | |
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Record in the Search Index
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| author | Tripathi, Suman Lata Saxena, Sobhit Sinha, Sanjeet Kumar Patel, Govind Singh |
| author_GND | (DE-588)1240855079 |
| author_facet | Tripathi, Suman Lata Saxena, Sobhit Sinha, Sanjeet Kumar Patel, Govind Singh |
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| author_sort | Tripathi, Suman Lata |
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| building | Verbundindex |
| bvnumber | BV047852359 |
| classification_rvk | ZN 4950 |
| ctrlnum | (OCoLC)1302313248 (DE-599)BVBBV047852359 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 1st edition |
| format | Book |
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| id | DE-604.BV047852359 |
| illustrated | Not Illustrated |
| index_date | 2024-07-03T19:15:02Z |
| indexdate | 2024-07-10T09:23:07Z |
| institution | BVB |
| isbn | 9781119778042 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-033235192 |
| oclc_num | 1302313248 |
| open_access_boolean | |
| owner | DE-1043 |
| owner_facet | DE-1043 |
| physical | XIV, 206 Seiten |
| publishDate | 2022 |
| publishDateSearch | 2022 |
| publishDateSort | 2022 |
| publisher | Wiley |
| record_format | marc |
| spelling | Tripathi, Suman Lata Verfasser (DE-588)1240855079 aut Digital VLSI Design and Simulation with Verilog Dr. Suman Lata Tripathi, Dr. Sobhit Saxena, Dr. Sanjeet Kumar Sinha, Dr. Govind Singh Patel 1st edition Hoboken Wiley 2022 XIV, 206 Seiten txt rdacontent n rdamedia nc rdacarrier VLSI (DE-588)4117388-0 gnd rswk-swf VERILOG (DE-588)4268385-3 gnd rswk-swf VLSI (DE-588)4117388-0 s VERILOG (DE-588)4268385-3 s DE-604 Saxena, Sobhit Verfasser aut Sinha, Sanjeet Kumar Verfasser aut Patel, Govind Singh Verfasser aut |
| spellingShingle | Tripathi, Suman Lata Saxena, Sobhit Sinha, Sanjeet Kumar Patel, Govind Singh Digital VLSI Design and Simulation with Verilog VLSI (DE-588)4117388-0 gnd VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4268385-3 |
| title | Digital VLSI Design and Simulation with Verilog |
| title_auth | Digital VLSI Design and Simulation with Verilog |
| title_exact_search | Digital VLSI Design and Simulation with Verilog |
| title_exact_search_txtP | Digital VLSI Design and Simulation with Verilog |
| title_full | Digital VLSI Design and Simulation with Verilog Dr. Suman Lata Tripathi, Dr. Sobhit Saxena, Dr. Sanjeet Kumar Sinha, Dr. Govind Singh Patel |
| title_fullStr | Digital VLSI Design and Simulation with Verilog Dr. Suman Lata Tripathi, Dr. Sobhit Saxena, Dr. Sanjeet Kumar Sinha, Dr. Govind Singh Patel |
| title_full_unstemmed | Digital VLSI Design and Simulation with Verilog Dr. Suman Lata Tripathi, Dr. Sobhit Saxena, Dr. Sanjeet Kumar Sinha, Dr. Govind Singh Patel |
| title_short | Digital VLSI Design and Simulation with Verilog |
| title_sort | digital vlsi design and simulation with verilog |
| topic | VLSI (DE-588)4117388-0 gnd VERILOG (DE-588)4268385-3 gnd |
| topic_facet | VLSI VERILOG |
| work_keys_str_mv | AT tripathisumanlata digitalvlsidesignandsimulationwithverilog AT saxenasobhit digitalvlsidesignandsimulationwithverilog AT sinhasanjeetkumar digitalvlsidesignandsimulationwithverilog AT patelgovindsingh digitalvlsidesignandsimulationwithverilog |