Architectures and theoretical models for shared scratchpad memory systems:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
Dresden
Jörg Vogt Verlag
2021
|
| Schriftenreihe: | Beiträge aus der Informationstechnik. Mobile Nachrichtenübertragung
Nr. 92 |
| Schlagworte: | |
| Online-Zugang: | Ausführliche Beschreibung Inhaltsverzeichnis |
| Beschreibung: | xi, 126 Seiten Illustrationen, Diagramme 21 cm x 14.8 cm |
| ISBN: | 9783959470506 3959470509 |
Internformat
MARC
| LEADER | 00000nam a22000008cb4500 | ||
|---|---|---|---|
| 001 | BV047627038 | ||
| 003 | DE-604 | ||
| 005 | 20220113 | ||
| 007 | t | ||
| 008 | 211206s2021 gw a||| m||| 00||| eng d | ||
| 015 | |a 21,N40 |2 dnb | ||
| 016 | 7 | |a 1242341218 |2 DE-101 | |
| 020 | |a 9783959470506 |c Broschur : EUR 69.00 (DE), EUR 71.00 (AT) |9 978-3-95947-050-6 | ||
| 020 | |a 3959470509 |9 3-95947-050-9 | ||
| 024 | 3 | |a 9783959470506 | |
| 035 | |a (OCoLC)1287946489 | ||
| 035 | |a (DE-599)DNB1242341218 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 044 | |a gw |c XA-DE-SN | ||
| 049 | |a DE-83 | ||
| 084 | |a ZN 5640 |0 (DE-625)157473: |2 rvk | ||
| 084 | |a ZN 4952 |0 (DE-625)157425: |2 rvk | ||
| 084 | |8 1\p |a 621.3 |2 23sdnb | ||
| 100 | 1 | |a Wittig, Robert |d 1989- |e Verfasser |0 (DE-588)1247032310 |4 aut | |
| 245 | 1 | 0 | |a Architectures and theoretical models for shared scratchpad memory systems |c Robert Wittig |
| 264 | 1 | |a Dresden |b Jörg Vogt Verlag |c 2021 | |
| 300 | |a xi, 126 Seiten |b Illustrationen, Diagramme |c 21 cm x 14.8 cm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Beiträge aus der Informationstechnik. Mobile Nachrichtenübertragung |v Nr. 92 | |
| 502 | |b Dissertation |c TU Dresden |d 2021 | ||
| 650 | 0 | 7 | |a Speicherzugriff |0 (DE-588)4182148-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Scratchpad-Architektur |0 (DE-588)1267704810 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Mehrkernprozessor |0 (DE-588)7598578-0 |2 gnd |9 rswk-swf |
| 653 | |a Chip | ||
| 653 | |a AIP | ||
| 653 | |a Memory | ||
| 655 | 7 | |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
| 689 | 0 | 0 | |a Scratchpad-Architektur |0 (DE-588)1267704810 |D s |
| 689 | 0 | 1 | |a Speicherzugriff |0 (DE-588)4182148-8 |D s |
| 689 | 0 | 2 | |a Mehrkernprozessor |0 (DE-588)7598578-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 830 | 0 | |a Beiträge aus der Informationstechnik. Mobile Nachrichtenübertragung |v Nr. 92 |w (DE-604)BV036860359 |9 92 | |
| 856 | 4 | 2 | |m X:MVB |q text/html |u http://www.vogtverlag.de/wissenschaft.html |3 Ausführliche Beschreibung |
| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=033011522&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-033011522 | ||
| 883 | 1 | |8 1\p |a vlb |d 20211002 |q DE-101 |u https://d-nb.info/provenance/plan#vlb | |
Datensatz im Suchindex
| _version_ | 1804183069874192384 |
|---|---|
| adam_text | CONTENTS
ABSTRACT
III
KURZFASSUNG
V
ACKNOWLEDGEMENT
VII
CONTENTS
IX
1
INTRODUCTION
1
1.1
RELATED
WORK
AND
CONTRIBUTION
............................................................
2
1.2
OUTLINE
...................................................................................................
5
2
BASIC
CONCEPTS
7
2.1
SYSTEM
CONCEPTS
....................................................................................
7
2.2
SYSTEM
MODEL
..........................................................................................
9
2.3
THE
ORIGIN
OF
ACCESS
CONFLICTS
...............................................................
10
2.4
THE
IMPLICATIONS
OF
MEMORY
AND
DATA
SHARING
....................................
11
3
A
FAST
AND
VERSATILE
MEMORY
ARCHITECTURE
15
3.1
REQUIREMENTS
..........................................................................................
15
3.2
STATE
OF
THE
ART
-
HARDWARE
PLATFORMS
.................................................
17
3.3
A
QUEUE-BASED
MEMORY
MANAGEMENT
SYSTEM
....................................
19
3.3.1
THE
INTERCONNECT
........................................................................
19
3.3.2
THE
MEMORY
CONTROLLER
............................................................
21
3.3.3
PROPERTIES
OF
THE
QMMU
ARCHITECTURE
.......................................
23
3.4
SYSTEM
ANALYSIS
........................................................................................
23
3.4.1
IMPLEMENTATION
...........................................................................
24
3.4.2
QMMU
AREA
AND
COST
ANALYSIS
................................................
26
3.4.3
CONFLICT
EVALUATION
.....................................................................
28
3.5
FUTURE
PROSPECTS
-
PARALLEL
TREES
.............................................................
28
3.6
SUMMARY
................................................................................................
29
4.1
GAINS
AND
LIMITS
OF
AIP
........................................................................
31
4.2
STATE
OF
THE
ART
-
CONFLICT
AVOIDANCE
AND
PREDICTION
METHODS
............
34
4.3
SECURITY
CONCERNS
....................................................................................
35
4.4
THEORY
OF
AIP
...........................................................................................
36
4.5
SUMMARY
.................................................................................................
38
5
BASIC
PREDICTORS
39
5.1
ACCESS
TIME
ANALYSIS
.............................................................................
39
5.1.1
THE
PROCESSOR
...............................................................................
39
5.1.2
THE
MIBENCH
...............................................................................
39
5.2
BASIC
PREDICTION
METHODS
........................................................................
41
5.2.1
ACCESS-LOOKAHEAD
BUFFER
............................................................
41
5.2.2
STATISTICAL
PREDICTORS
..................................................................
45
5.3
SUMMARY
.................................................................................................
49
6
ADVANCED
PREDICTORS
51
6.1
HASHED
MAXIMUM-A-POSTERIORI
PREDICTOR
.............................................
51
6.2
TAGE
PREDICTOR
........................................................................................
53
6.2.1
PREDICTION
BY
PARTIAL
MATCHING
...................................................
53
6.2.2
PPM
FOR
AIP
.................................................................................
56
6.2.3
FROM
PPM
TO
TAGE
.....................................................................
56
6.2.4
IMPLEMENTATION
...........................................................................
58
6.2.5
PERFORMANCE
AND
COST
...............................................................
65
6.3
PREDICTOR
COMPARISON
............................................................................
67
6.4
SUMMARY
.................................................................................................
68
7
MODEL
BASED
THROUGHPUT
ESTIMATION
71
7.1
SYSTEM
MODEL
...........................................................................................
72
7.2
STATE
OF
THE
ART
-
THROUGHPUT
ESTIMATION
.............................................
74
7.3
THE
OCCUPANCY
MODEL
...........................................................................
75
7.3.1
INCLUDING
NON-UNIFORM
ACCESS
PROBABILITIES
...........................
76
7.3.2
DERIVING
SERVICE
RATIOS
...............................................................
76
7.3.3
INCLUDING
PRIORITIES
.....................................................................
77
7.4
THE
PRIORITY
MODEL
..................................................................................
78
7.4.1
INCLUDING
NON-UNIFORM
ACCESS
PROBABILITIES
...........................
78
7.4.2
INCLUDING
ARBITRARY
PRIORITIES
....................................................
78
7.5
THE
MARKOV
MODEL
.................................................................................
79
7.5.1
INCLUDING
NON-UNIFORM
ACCESS
PROBABILITIES
............................
81
7.5.2
DERIVING
SERVICE
RATIOS
...............................................................
82
7.5.3
INCLUDING
PRIORITIES
......................................................................
83
7.F
EVALUATION
................................................................................................
84
7.6.1
PERFORMANCE
OF
THE
ORIGINAL
MODELS
..........................................
84
7.6.2
PERFORMANCE
WITH
NON-UNIFORM
ACCESS
PROBABILITIES
...............
86
7.6.3
PERFORMANCE
WITH
PROCESSOR
PRIORITIES
........................................
89
7.7
ADAPTATIONS
FOR
THE
QMMU-SYSTEM
......................................................
89
7.8
SUMMARY
................................................................................................
92
8
DESIGN
CONSIDERATIONS
93
8.1
DESIGNFLOW
.............................................................................................
93
8.2
EXAMPLE
DESIGN
.......................................................................................
94
9
CONCLUSION
97
APPENDIX
A
INTERCONNECT
LAYOUTS
99
APPENDIX
B
CPUSPEC
BENCHMARK
101
APPENDIX
C
HASH
GENERATION
103
LIST
OF
ABBREVIATIONS
105
LIST
OF
SYMBOLS
107
LIST
OF
FIGURES
111
LIST
OF
TABLES
115
BIBLIOGRAPHY
117
PUBLICATIONS
OF
THE
AUTHOR
125
|
| adam_txt |
CONTENTS
ABSTRACT
III
KURZFASSUNG
V
ACKNOWLEDGEMENT
VII
CONTENTS
IX
1
INTRODUCTION
1
1.1
RELATED
WORK
AND
CONTRIBUTION
.
2
1.2
OUTLINE
.
5
2
BASIC
CONCEPTS
7
2.1
SYSTEM
CONCEPTS
.
7
2.2
SYSTEM
MODEL
.
9
2.3
THE
ORIGIN
OF
ACCESS
CONFLICTS
.
10
2.4
THE
IMPLICATIONS
OF
MEMORY
AND
DATA
SHARING
.
11
3
A
FAST
AND
VERSATILE
MEMORY
ARCHITECTURE
15
3.1
REQUIREMENTS
.
15
3.2
STATE
OF
THE
ART
-
HARDWARE
PLATFORMS
.
17
3.3
A
QUEUE-BASED
MEMORY
MANAGEMENT
SYSTEM
.
19
3.3.1
THE
INTERCONNECT
.
19
3.3.2
THE
MEMORY
CONTROLLER
.
21
3.3.3
PROPERTIES
OF
THE
QMMU
ARCHITECTURE
.
23
3.4
SYSTEM
ANALYSIS
.
23
3.4.1
IMPLEMENTATION
.
24
3.4.2
QMMU
AREA
AND
COST
ANALYSIS
.
26
3.4.3
CONFLICT
EVALUATION
.
28
3.5
FUTURE
PROSPECTS
-
PARALLEL
TREES
.
28
3.6
SUMMARY
.
29
4.1
GAINS
AND
LIMITS
OF
AIP
.
31
4.2
STATE
OF
THE
ART
-
CONFLICT
AVOIDANCE
AND
PREDICTION
METHODS
.
34
4.3
SECURITY
CONCERNS
.
35
4.4
THEORY
OF
AIP
.
36
4.5
SUMMARY
.
38
5
BASIC
PREDICTORS
39
5.1
ACCESS
TIME
ANALYSIS
.
39
5.1.1
THE
PROCESSOR
.
39
5.1.2
THE
MIBENCH
.
39
5.2
BASIC
PREDICTION
METHODS
.
41
5.2.1
ACCESS-LOOKAHEAD
BUFFER
.
41
5.2.2
STATISTICAL
PREDICTORS
.
45
5.3
SUMMARY
.
49
6
ADVANCED
PREDICTORS
51
6.1
HASHED
MAXIMUM-A-POSTERIORI
PREDICTOR
.
51
6.2
TAGE
PREDICTOR
.
53
6.2.1
PREDICTION
BY
PARTIAL
MATCHING
.
53
6.2.2
PPM
FOR
AIP
.
56
6.2.3
FROM
PPM
TO
TAGE
.
56
6.2.4
IMPLEMENTATION
.
58
6.2.5
PERFORMANCE
AND
COST
.
65
6.3
PREDICTOR
COMPARISON
.
67
6.4
SUMMARY
.
68
7
MODEL
BASED
THROUGHPUT
ESTIMATION
71
7.1
SYSTEM
MODEL
.
72
7.2
STATE
OF
THE
ART
-
THROUGHPUT
ESTIMATION
.
74
7.3
THE
OCCUPANCY
MODEL
.
75
7.3.1
INCLUDING
NON-UNIFORM
ACCESS
PROBABILITIES
.
76
7.3.2
DERIVING
SERVICE
RATIOS
.
76
7.3.3
INCLUDING
PRIORITIES
.
77
7.4
THE
PRIORITY
MODEL
.
78
7.4.1
INCLUDING
NON-UNIFORM
ACCESS
PROBABILITIES
.
78
7.4.2
INCLUDING
ARBITRARY
PRIORITIES
.
78
7.5
THE
MARKOV
MODEL
.
79
7.5.1
INCLUDING
NON-UNIFORM
ACCESS
PROBABILITIES
.
81
7.5.2
DERIVING
SERVICE
RATIOS
.
82
7.5.3
INCLUDING
PRIORITIES
.
83
7.F
EVALUATION
.
84
7.6.1
PERFORMANCE
OF
THE
ORIGINAL
MODELS
.
84
7.6.2
PERFORMANCE
WITH
NON-UNIFORM
ACCESS
PROBABILITIES
.
86
7.6.3
PERFORMANCE
WITH
PROCESSOR
PRIORITIES
.
89
7.7
ADAPTATIONS
FOR
THE
QMMU-SYSTEM
.
89
7.8
SUMMARY
.
92
8
DESIGN
CONSIDERATIONS
93
8.1
DESIGNFLOW
.
93
8.2
EXAMPLE
DESIGN
.
94
9
CONCLUSION
97
APPENDIX
A
INTERCONNECT
LAYOUTS
99
APPENDIX
B
CPUSPEC
BENCHMARK
101
APPENDIX
C
HASH
GENERATION
103
LIST
OF
ABBREVIATIONS
105
LIST
OF
SYMBOLS
107
LIST
OF
FIGURES
111
LIST
OF
TABLES
115
BIBLIOGRAPHY
117
PUBLICATIONS
OF
THE
AUTHOR
125 |
| any_adam_object | 1 |
| any_adam_object_boolean | 1 |
| author | Wittig, Robert 1989- |
| author_GND | (DE-588)1247032310 |
| author_facet | Wittig, Robert 1989- |
| author_role | aut |
| author_sort | Wittig, Robert 1989- |
| author_variant | r w rw |
| building | Verbundindex |
| bvnumber | BV047627038 |
| classification_rvk | ZN 5640 ZN 4952 |
| ctrlnum | (OCoLC)1287946489 (DE-599)DNB1242341218 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Thesis Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02366nam a22005538cb4500</leader><controlfield tag="001">BV047627038</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20220113 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">211206s2021 gw a||| m||| 00||| eng d</controlfield><datafield tag="015" ind1=" " ind2=" "><subfield code="a">21,N40</subfield><subfield code="2">dnb</subfield></datafield><datafield tag="016" ind1="7" ind2=" "><subfield code="a">1242341218</subfield><subfield code="2">DE-101</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9783959470506</subfield><subfield code="c">Broschur : EUR 69.00 (DE), EUR 71.00 (AT)</subfield><subfield code="9">978-3-95947-050-6</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">3959470509</subfield><subfield code="9">3-95947-050-9</subfield></datafield><datafield tag="024" ind1="3" ind2=" "><subfield code="a">9783959470506</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1287946489</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)DNB1242341218</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">gw</subfield><subfield code="c">XA-DE-SN</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-83</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 5640</subfield><subfield code="0">(DE-625)157473:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4952</subfield><subfield code="0">(DE-625)157425:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="8">1\p</subfield><subfield code="a">621.3</subfield><subfield code="2">23sdnb</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Wittig, Robert</subfield><subfield code="d">1989-</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)1247032310</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Architectures and theoretical models for shared scratchpad memory systems</subfield><subfield code="c">Robert Wittig</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Dresden</subfield><subfield code="b">Jörg Vogt Verlag</subfield><subfield code="c">2021</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">xi, 126 Seiten</subfield><subfield code="b">Illustrationen, Diagramme</subfield><subfield code="c">21 cm x 14.8 cm</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Beiträge aus der Informationstechnik. Mobile Nachrichtenübertragung</subfield><subfield code="v">Nr. 92</subfield></datafield><datafield tag="502" ind1=" " ind2=" "><subfield code="b">Dissertation</subfield><subfield code="c">TU Dresden</subfield><subfield code="d">2021</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Speicherzugriff</subfield><subfield code="0">(DE-588)4182148-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Scratchpad-Architektur</subfield><subfield code="0">(DE-588)1267704810</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Mehrkernprozessor</subfield><subfield code="0">(DE-588)7598578-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Chip</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">AIP</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Memory</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)4113937-9</subfield><subfield code="a">Hochschulschrift</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Scratchpad-Architektur</subfield><subfield code="0">(DE-588)1267704810</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Speicherzugriff</subfield><subfield code="0">(DE-588)4182148-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">Mehrkernprozessor</subfield><subfield code="0">(DE-588)7598578-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Beiträge aus der Informationstechnik. Mobile Nachrichtenübertragung</subfield><subfield code="v">Nr. 92</subfield><subfield code="w">(DE-604)BV036860359</subfield><subfield code="9">92</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">X:MVB</subfield><subfield code="q">text/html</subfield><subfield code="u">http://www.vogtverlag.de/wissenschaft.html</subfield><subfield code="3">Ausführliche Beschreibung</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">DNB Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=033011522&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-033011522</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">vlb</subfield><subfield code="d">20211002</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#vlb</subfield></datafield></record></collection> |
| genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV047627038 |
| illustrated | Illustrated |
| index_date | 2024-07-03T18:44:33Z |
| indexdate | 2024-07-10T09:17:35Z |
| institution | BVB |
| isbn | 9783959470506 3959470509 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-033011522 |
| oclc_num | 1287946489 |
| open_access_boolean | |
| owner | DE-83 |
| owner_facet | DE-83 |
| physical | xi, 126 Seiten Illustrationen, Diagramme 21 cm x 14.8 cm |
| publishDate | 2021 |
| publishDateSearch | 2021 |
| publishDateSort | 2021 |
| publisher | Jörg Vogt Verlag |
| record_format | marc |
| series | Beiträge aus der Informationstechnik. Mobile Nachrichtenübertragung |
| series2 | Beiträge aus der Informationstechnik. Mobile Nachrichtenübertragung |
| spelling | Wittig, Robert 1989- Verfasser (DE-588)1247032310 aut Architectures and theoretical models for shared scratchpad memory systems Robert Wittig Dresden Jörg Vogt Verlag 2021 xi, 126 Seiten Illustrationen, Diagramme 21 cm x 14.8 cm txt rdacontent n rdamedia nc rdacarrier Beiträge aus der Informationstechnik. Mobile Nachrichtenübertragung Nr. 92 Dissertation TU Dresden 2021 Speicherzugriff (DE-588)4182148-8 gnd rswk-swf Scratchpad-Architektur (DE-588)1267704810 gnd rswk-swf Mehrkernprozessor (DE-588)7598578-0 gnd rswk-swf Chip AIP Memory (DE-588)4113937-9 Hochschulschrift gnd-content Scratchpad-Architektur (DE-588)1267704810 s Speicherzugriff (DE-588)4182148-8 s Mehrkernprozessor (DE-588)7598578-0 s DE-604 Beiträge aus der Informationstechnik. Mobile Nachrichtenübertragung Nr. 92 (DE-604)BV036860359 92 X:MVB text/html http://www.vogtverlag.de/wissenschaft.html Ausführliche Beschreibung DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=033011522&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p vlb 20211002 DE-101 https://d-nb.info/provenance/plan#vlb |
| spellingShingle | Wittig, Robert 1989- Architectures and theoretical models for shared scratchpad memory systems Beiträge aus der Informationstechnik. Mobile Nachrichtenübertragung Speicherzugriff (DE-588)4182148-8 gnd Scratchpad-Architektur (DE-588)1267704810 gnd Mehrkernprozessor (DE-588)7598578-0 gnd |
| subject_GND | (DE-588)4182148-8 (DE-588)1267704810 (DE-588)7598578-0 (DE-588)4113937-9 |
| title | Architectures and theoretical models for shared scratchpad memory systems |
| title_auth | Architectures and theoretical models for shared scratchpad memory systems |
| title_exact_search | Architectures and theoretical models for shared scratchpad memory systems |
| title_exact_search_txtP | Architectures and theoretical models for shared scratchpad memory systems |
| title_full | Architectures and theoretical models for shared scratchpad memory systems Robert Wittig |
| title_fullStr | Architectures and theoretical models for shared scratchpad memory systems Robert Wittig |
| title_full_unstemmed | Architectures and theoretical models for shared scratchpad memory systems Robert Wittig |
| title_short | Architectures and theoretical models for shared scratchpad memory systems |
| title_sort | architectures and theoretical models for shared scratchpad memory systems |
| topic | Speicherzugriff (DE-588)4182148-8 gnd Scratchpad-Architektur (DE-588)1267704810 gnd Mehrkernprozessor (DE-588)7598578-0 gnd |
| topic_facet | Speicherzugriff Scratchpad-Architektur Mehrkernprozessor Hochschulschrift |
| url | http://www.vogtverlag.de/wissenschaft.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=033011522&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV036860359 |
| work_keys_str_mv | AT wittigrobert architecturesandtheoreticalmodelsforsharedscratchpadmemorysystems |