Dual port SRAM - sensing scheme:
Course content reaffirmed: 06/2015--This dual port SRAM utilizes a 2-sided differential sensing scheme by taking advantage of the fact that both bit true and bit complement bit lines are available due to the nature of the 6T SRAM bit cell. The sense amp is clocked by a 1 of 4 decoded Sense Amp Clock...
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| Main Author: | |
|---|---|
| Format: | Electronic Video |
| Language: | English |
| Published: |
United States
IEEE
2011
|
| Subjects: | |
| Online Access: | FHN01 TUM01 |
| Summary: | Course content reaffirmed: 06/2015--This dual port SRAM utilizes a 2-sided differential sensing scheme by taking advantage of the fact that both bit true and bit complement bit lines are available due to the nature of the 6T SRAM bit cell. The sense amp is clocked by a 1 of 4 decoded Sense Amp Clock utilizing a regenerative feedback latch that can generate a logic output that is rail to rail. The read path from the bit line through the read select circuitry to the amplification of the signal at the sense amp output is presented in this tutorial |
| Item Description: | Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020) |
| Physical Description: | 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations |
Staff View
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| spelling | Sheppard, Doug Verfasser aut Dual port SRAM - sensing scheme Doug Sheppard Dual port static random-access memory - sensing scheme United States IEEE 2011 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations tdi rdacontent c rdamedia cr rdacarrier Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020) Course content reaffirmed: 06/2015--This dual port SRAM utilizes a 2-sided differential sensing scheme by taking advantage of the fact that both bit true and bit complement bit lines are available due to the nature of the 6T SRAM bit cell. The sense amp is clocked by a 1 of 4 decoded Sense Amp Clock utilizing a regenerative feedback latch that can generate a logic output that is rail to rail. The read path from the bit line through the read select circuitry to the amplification of the signal at the sense amp output is presented in this tutorial Random access memory Synchronization (DE-588)4017102-4 Film gnd-content |
| spellingShingle | Sheppard, Doug Dual port SRAM - sensing scheme Random access memory Synchronization |
| subject_GND | (DE-588)4017102-4 |
| title | Dual port SRAM - sensing scheme |
| title_alt | Dual port static random-access memory - sensing scheme |
| title_auth | Dual port SRAM - sensing scheme |
| title_exact_search | Dual port SRAM - sensing scheme |
| title_exact_search_txtP | Dual port SRAM - sensing scheme |
| title_full | Dual port SRAM - sensing scheme Doug Sheppard |
| title_fullStr | Dual port SRAM - sensing scheme Doug Sheppard |
| title_full_unstemmed | Dual port SRAM - sensing scheme Doug Sheppard |
| title_short | Dual port SRAM - sensing scheme |
| title_sort | dual port sram sensing scheme |
| topic | Random access memory Synchronization |
| topic_facet | Random access memory Synchronization Film |
| work_keys_str_mv | AT shepparddoug dualportsramsensingscheme AT shepparddoug dualportstaticrandomaccessmemorysensingscheme |