Dual port SRAM - sensing scheme:
Course content reaffirmed: 06/2015--This dual port SRAM utilizes a 2-sided differential sensing scheme by taking advantage of the fact that both bit true and bit complement bit lines are available due to the nature of the 6T SRAM bit cell. The sense amp is clocked by a 1 of 4 decoded Sense Amp Clock...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch Video |
| Sprache: | English |
| Veröffentlicht: |
United States
IEEE
2011
|
| Schlagworte: | |
| Online-Zugang: | FHN01 TUM01 |
| Zusammenfassung: | Course content reaffirmed: 06/2015--This dual port SRAM utilizes a 2-sided differential sensing scheme by taking advantage of the fact that both bit true and bit complement bit lines are available due to the nature of the 6T SRAM bit cell. The sense amp is clocked by a 1 of 4 decoded Sense Amp Clock utilizing a regenerative feedback latch that can generate a logic output that is rail to rail. The read path from the bit line through the read select circuitry to the amplification of the signal at the sense amp output is presented in this tutorial |
| Beschreibung: | Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020) |
| Beschreibung: | 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV047477160 | ||
| 003 | DE-604 | ||
| 005 | 20220216 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 210921s2011 |||| o||u| ||||||eng d | ||
| 020 | |z 978161284523 |9 978161284523 | ||
| 035 | |a (ZDB-37-ICG)EDP237 | ||
| 035 | |a (OCoLC)1269396818 | ||
| 035 | |a (DE-599)BVBBV047477160 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91 |a DE-92 | ||
| 082 | 0 | |a 621.38195833 |2 23 | |
| 100 | 1 | |a Sheppard, Doug |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Dual port SRAM - sensing scheme |c Doug Sheppard |
| 246 | 1 | 3 | |a Dual port static random-access memory - sensing scheme |
| 264 | 1 | |a United States |b IEEE |c 2011 | |
| 300 | |a 1 Online-Resource (1 Videodatei, 60 Minuten) |b color illustrations | ||
| 336 | |b tdi |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020) | ||
| 520 | |a Course content reaffirmed: 06/2015--This dual port SRAM utilizes a 2-sided differential sensing scheme by taking advantage of the fact that both bit true and bit complement bit lines are available due to the nature of the 6T SRAM bit cell. The sense amp is clocked by a 1 of 4 decoded Sense Amp Clock utilizing a regenerative feedback latch that can generate a logic output that is rail to rail. The read path from the bit line through the read select circuitry to the amplification of the signal at the sense amp output is presented in this tutorial | ||
| 650 | 4 | |a Random access memory | |
| 650 | 4 | |a Synchronization | |
| 655 | 7 | |0 (DE-588)4017102-4 |a Film |2 gnd-content | |
| 912 | |a ZDB-37-ICG | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-032878721 | ||
| 966 | e | |u https://ieeexplore.ieee.org/courses/details/EDP237 |l FHN01 |p ZDB-37-ICG |x Verlag |3 Volltext | |
| 966 | e | |u https://ieeexplore.ieee.org/courses/details/EDP237 |l TUM01 |p ZDB-37-ICG |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804182793148694528 |
|---|---|
| adam_txt | |
| any_adam_object | |
| any_adam_object_boolean | |
| author | Sheppard, Doug |
| author_facet | Sheppard, Doug |
| author_role | aut |
| author_sort | Sheppard, Doug |
| author_variant | d s ds |
| building | Verbundindex |
| bvnumber | BV047477160 |
| collection | ZDB-37-ICG |
| ctrlnum | (ZDB-37-ICG)EDP237 (OCoLC)1269396818 (DE-599)BVBBV047477160 |
| dewey-full | 621.38195833 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.38195833 |
| dewey-search | 621.38195833 |
| dewey-sort | 3621.38195833 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic Video |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01951nmm a2200385zc 4500</leader><controlfield tag="001">BV047477160</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20220216 </controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">210921s2011 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="z">978161284523</subfield><subfield code="9">978161284523</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-37-ICG)EDP237</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1269396818</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV047477160</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91</subfield><subfield code="a">DE-92</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.38195833</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Sheppard, Doug</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Dual port SRAM - sensing scheme</subfield><subfield code="c">Doug Sheppard</subfield></datafield><datafield tag="246" ind1="1" ind2="3"><subfield code="a">Dual port static random-access memory - sensing scheme</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">United States</subfield><subfield code="b">IEEE</subfield><subfield code="c">2011</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Resource (1 Videodatei, 60 Minuten)</subfield><subfield code="b">color illustrations</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">tdi</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020)</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Course content reaffirmed: 06/2015--This dual port SRAM utilizes a 2-sided differential sensing scheme by taking advantage of the fact that both bit true and bit complement bit lines are available due to the nature of the 6T SRAM bit cell. The sense amp is clocked by a 1 of 4 decoded Sense Amp Clock utilizing a regenerative feedback latch that can generate a logic output that is rail to rail. The read path from the bit line through the read select circuitry to the amplification of the signal at the sense amp output is presented in this tutorial</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Random access memory</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Synchronization</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)4017102-4</subfield><subfield code="a">Film</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-37-ICG</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-032878721</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://ieeexplore.ieee.org/courses/details/EDP237</subfield><subfield code="l">FHN01</subfield><subfield code="p">ZDB-37-ICG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://ieeexplore.ieee.org/courses/details/EDP237</subfield><subfield code="l">TUM01</subfield><subfield code="p">ZDB-37-ICG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| genre | (DE-588)4017102-4 Film gnd-content |
| genre_facet | Film |
| id | DE-604.BV047477160 |
| illustrated | Illustrated |
| index_date | 2024-07-03T18:11:31Z |
| indexdate | 2024-07-10T09:13:11Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-032878721 |
| oclc_num | 1269396818 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-92 |
| owner_facet | DE-91 DE-BY-TUM DE-92 |
| physical | 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations |
| psigel | ZDB-37-ICG |
| publishDate | 2011 |
| publishDateSearch | 2011 |
| publishDateSort | 2011 |
| publisher | IEEE |
| record_format | marc |
| spelling | Sheppard, Doug Verfasser aut Dual port SRAM - sensing scheme Doug Sheppard Dual port static random-access memory - sensing scheme United States IEEE 2011 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations tdi rdacontent c rdamedia cr rdacarrier Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020) Course content reaffirmed: 06/2015--This dual port SRAM utilizes a 2-sided differential sensing scheme by taking advantage of the fact that both bit true and bit complement bit lines are available due to the nature of the 6T SRAM bit cell. The sense amp is clocked by a 1 of 4 decoded Sense Amp Clock utilizing a regenerative feedback latch that can generate a logic output that is rail to rail. The read path from the bit line through the read select circuitry to the amplification of the signal at the sense amp output is presented in this tutorial Random access memory Synchronization (DE-588)4017102-4 Film gnd-content |
| spellingShingle | Sheppard, Doug Dual port SRAM - sensing scheme Random access memory Synchronization |
| subject_GND | (DE-588)4017102-4 |
| title | Dual port SRAM - sensing scheme |
| title_alt | Dual port static random-access memory - sensing scheme |
| title_auth | Dual port SRAM - sensing scheme |
| title_exact_search | Dual port SRAM - sensing scheme |
| title_exact_search_txtP | Dual port SRAM - sensing scheme |
| title_full | Dual port SRAM - sensing scheme Doug Sheppard |
| title_fullStr | Dual port SRAM - sensing scheme Doug Sheppard |
| title_full_unstemmed | Dual port SRAM - sensing scheme Doug Sheppard |
| title_short | Dual port SRAM - sensing scheme |
| title_sort | dual port sram sensing scheme |
| topic | Random access memory Synchronization |
| topic_facet | Random access memory Synchronization Film |
| work_keys_str_mv | AT shepparddoug dualportsramsensingscheme AT shepparddoug dualportstaticrandomaccessmemorysensingscheme |