Dual port SRAM - SPICE simulation model of array:
Course content reaffirmed: 06/2015--In memory design it is vitally important that the array be modeled in SPICE very accurately. This is required for proper analysis of: design margin, timing, performance, power and overall characterization of the design. Since a memory can have millions of memory c...
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Elektronisch Video |
| Sprache: | English |
| Veröffentlicht: |
United States
IEEE
2011
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| Schlagworte: | |
| Online-Zugang: | FHN01 TUM01 |
| Zusammenfassung: | Course content reaffirmed: 06/2015--In memory design it is vitally important that the array be modeled in SPICE very accurately. This is required for proper analysis of: design margin, timing, performance, power and overall characterization of the design. Since a memory can have millions of memory cells (bit cells) it is unpractical to include every cell in the SPICE simulation as it would be too large and make the simulation time very long. This tutorial presents a method of modeling the array loading of the bit lines and word lines utilizing the mult factor in SPICE without compromising the accuracy of the simulation. The overall architecture of the chip layout is analyzed to determine the best approach for the particular configuration of the memory |
| Beschreibung: | Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020) |
| Beschreibung: | 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations |
| ISBN: | 9781612845142 |
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| isbn | 9781612845142 |
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| spelling | Sheppard, Doug Verfasser aut Dual port SRAM - SPICE simulation model of array Doug Sheppard Dual port static random-access memory - SPICE simulation model of array Dual port static random-access memory - simulation program with integrated circuit emphasis simulation model of array United States IEEE 2011 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations tdi rdacontent c rdamedia cr rdacarrier Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020) Course content reaffirmed: 06/2015--In memory design it is vitally important that the array be modeled in SPICE very accurately. This is required for proper analysis of: design margin, timing, performance, power and overall characterization of the design. Since a memory can have millions of memory cells (bit cells) it is unpractical to include every cell in the SPICE simulation as it would be too large and make the simulation time very long. This tutorial presents a method of modeling the array loading of the bit lines and word lines utilizing the mult factor in SPICE without compromising the accuracy of the simulation. The overall architecture of the chip layout is analyzed to determine the best approach for the particular configuration of the memory Random access memory (DE-588)4017102-4 Film gnd-content |
| spellingShingle | Sheppard, Doug Dual port SRAM - SPICE simulation model of array Random access memory |
| subject_GND | (DE-588)4017102-4 |
| title | Dual port SRAM - SPICE simulation model of array |
| title_alt | Dual port static random-access memory - SPICE simulation model of array Dual port static random-access memory - simulation program with integrated circuit emphasis simulation model of array |
| title_auth | Dual port SRAM - SPICE simulation model of array |
| title_exact_search | Dual port SRAM - SPICE simulation model of array |
| title_exact_search_txtP | Dual port SRAM - SPICE simulation model of array |
| title_full | Dual port SRAM - SPICE simulation model of array Doug Sheppard |
| title_fullStr | Dual port SRAM - SPICE simulation model of array Doug Sheppard |
| title_full_unstemmed | Dual port SRAM - SPICE simulation model of array Doug Sheppard |
| title_short | Dual port SRAM - SPICE simulation model of array |
| title_sort | dual port sram spice simulation model of array |
| topic | Random access memory |
| topic_facet | Random access memory Film |
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