Dual port SRAM design - chip plan and array configuration:
Course content reaffirmed: 06/2015--An important aspect of memory design is to translate the logical block diagram into a chip plan of the actual placement in layout of the key higher level cells and how they will interact with each other. The first place to start is with the configuration of the me...
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Elektronisch Video |
| Sprache: | English |
| Veröffentlicht: |
United States
IEEE
2011
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| Schlagworte: | |
| Online-Zugang: | FHN01 TUM01 |
| Zusammenfassung: | Course content reaffirmed: 06/2015--An important aspect of memory design is to translate the logical block diagram into a chip plan of the actual placement in layout of the key higher level cells and how they will interact with each other. The first place to start is with the configuration of the memory cell array in rows and columns which in turn will determine the column decode and row decode scheme. In the case of a dual port there are 2 sets of column decoders and 2 sets of row decoders - one for each port. The column decode must be chosen such that it selects the appropriate number of columns within the array that will result in the required bits per word (BPW) that the customer requires. This tutorial presents various array configurations and the relationship between the total bits, bits per word, number of rows and number of columns |
| Beschreibung: | Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020) |
| Beschreibung: | 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations |
| ISBN: | 9781612845135 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV047477147 | ||
| 003 | DE-604 | ||
| 005 | 20220216 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 210921s2011 |||| o||u| ||||||eng d | ||
| 020 | |a 9781612845135 |9 978-1-61284-513-5 | ||
| 035 | |a (ZDB-37-ICG)EDP222 | ||
| 035 | |a (OCoLC)1269397146 | ||
| 035 | |a (DE-599)BVBBV047477147 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91 |a DE-92 | ||
| 082 | 0 | |a 621.38195833 |2 23 | |
| 100 | 1 | |a Sheppard, Doug |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Dual port SRAM design - chip plan and array configuration |c Doug Sheppard |
| 246 | 1 | 3 | |a Dual port static random-access memory design - chip plan and array configuration |
| 264 | 1 | |a United States |b IEEE |c 2011 | |
| 300 | |a 1 Online-Resource (1 Videodatei, 60 Minuten) |b color illustrations | ||
| 336 | |b tdi |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020) | ||
| 520 | |a Course content reaffirmed: 06/2015--An important aspect of memory design is to translate the logical block diagram into a chip plan of the actual placement in layout of the key higher level cells and how they will interact with each other. The first place to start is with the configuration of the memory cell array in rows and columns which in turn will determine the column decode and row decode scheme. In the case of a dual port there are 2 sets of column decoders and 2 sets of row decoders - one for each port. The column decode must be chosen such that it selects the appropriate number of columns within the array that will result in the required bits per word (BPW) that the customer requires. This tutorial presents various array configurations and the relationship between the total bits, bits per word, number of rows and number of columns | ||
| 650 | 4 | |a Random access memory | |
| 650 | 4 | |a Computer architecture | |
| 650 | 4 | |a Configuration management | |
| 650 | 4 | |a Logic design | |
| 655 | 7 | |0 (DE-588)4017102-4 |a Film |2 gnd-content | |
| 912 | |a ZDB-37-ICG | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-032878708 | ||
| 966 | e | |u https://ieeexplore.ieee.org/courses/details/EDP222 |l FHN01 |p ZDB-37-ICG |x Verlag |3 Volltext | |
| 966 | e | |u https://ieeexplore.ieee.org/courses/details/EDP222 |l TUM01 |p ZDB-37-ICG |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804182793137160192 |
|---|---|
| adam_txt | |
| any_adam_object | |
| any_adam_object_boolean | |
| author | Sheppard, Doug |
| author_facet | Sheppard, Doug |
| author_role | aut |
| author_sort | Sheppard, Doug |
| author_variant | d s ds |
| building | Verbundindex |
| bvnumber | BV047477147 |
| collection | ZDB-37-ICG |
| ctrlnum | (ZDB-37-ICG)EDP222 (OCoLC)1269397146 (DE-599)BVBBV047477147 |
| dewey-full | 621.38195833 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.38195833 |
| dewey-search | 621.38195833 |
| dewey-sort | 3621.38195833 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic Video |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02386nmm a2200409zc 4500</leader><controlfield tag="001">BV047477147</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20220216 </controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">210921s2011 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781612845135</subfield><subfield code="9">978-1-61284-513-5</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-37-ICG)EDP222</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1269397146</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV047477147</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91</subfield><subfield code="a">DE-92</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.38195833</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Sheppard, Doug</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Dual port SRAM design - chip plan and array configuration</subfield><subfield code="c">Doug Sheppard</subfield></datafield><datafield tag="246" ind1="1" ind2="3"><subfield code="a">Dual port static random-access memory design - chip plan and array configuration</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">United States</subfield><subfield code="b">IEEE</subfield><subfield code="c">2011</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Resource (1 Videodatei, 60 Minuten)</subfield><subfield code="b">color illustrations</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">tdi</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020)</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Course content reaffirmed: 06/2015--An important aspect of memory design is to translate the logical block diagram into a chip plan of the actual placement in layout of the key higher level cells and how they will interact with each other. The first place to start is with the configuration of the memory cell array in rows and columns which in turn will determine the column decode and row decode scheme. In the case of a dual port there are 2 sets of column decoders and 2 sets of row decoders - one for each port. The column decode must be chosen such that it selects the appropriate number of columns within the array that will result in the required bits per word (BPW) that the customer requires. This tutorial presents various array configurations and the relationship between the total bits, bits per word, number of rows and number of columns</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Random access memory</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer architecture</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Configuration management</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Logic design</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)4017102-4</subfield><subfield code="a">Film</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-37-ICG</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-032878708</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://ieeexplore.ieee.org/courses/details/EDP222</subfield><subfield code="l">FHN01</subfield><subfield code="p">ZDB-37-ICG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://ieeexplore.ieee.org/courses/details/EDP222</subfield><subfield code="l">TUM01</subfield><subfield code="p">ZDB-37-ICG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| genre | (DE-588)4017102-4 Film gnd-content |
| genre_facet | Film |
| id | DE-604.BV047477147 |
| illustrated | Illustrated |
| index_date | 2024-07-03T18:11:31Z |
| indexdate | 2024-07-10T09:13:11Z |
| institution | BVB |
| isbn | 9781612845135 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-032878708 |
| oclc_num | 1269397146 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-92 |
| owner_facet | DE-91 DE-BY-TUM DE-92 |
| physical | 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations |
| psigel | ZDB-37-ICG |
| publishDate | 2011 |
| publishDateSearch | 2011 |
| publishDateSort | 2011 |
| publisher | IEEE |
| record_format | marc |
| spelling | Sheppard, Doug Verfasser aut Dual port SRAM design - chip plan and array configuration Doug Sheppard Dual port static random-access memory design - chip plan and array configuration United States IEEE 2011 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations tdi rdacontent c rdamedia cr rdacarrier Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020) Course content reaffirmed: 06/2015--An important aspect of memory design is to translate the logical block diagram into a chip plan of the actual placement in layout of the key higher level cells and how they will interact with each other. The first place to start is with the configuration of the memory cell array in rows and columns which in turn will determine the column decode and row decode scheme. In the case of a dual port there are 2 sets of column decoders and 2 sets of row decoders - one for each port. The column decode must be chosen such that it selects the appropriate number of columns within the array that will result in the required bits per word (BPW) that the customer requires. This tutorial presents various array configurations and the relationship between the total bits, bits per word, number of rows and number of columns Random access memory Computer architecture Configuration management Logic design (DE-588)4017102-4 Film gnd-content |
| spellingShingle | Sheppard, Doug Dual port SRAM design - chip plan and array configuration Random access memory Computer architecture Configuration management Logic design |
| subject_GND | (DE-588)4017102-4 |
| title | Dual port SRAM design - chip plan and array configuration |
| title_alt | Dual port static random-access memory design - chip plan and array configuration |
| title_auth | Dual port SRAM design - chip plan and array configuration |
| title_exact_search | Dual port SRAM design - chip plan and array configuration |
| title_exact_search_txtP | Dual port SRAM design - chip plan and array configuration |
| title_full | Dual port SRAM design - chip plan and array configuration Doug Sheppard |
| title_fullStr | Dual port SRAM design - chip plan and array configuration Doug Sheppard |
| title_full_unstemmed | Dual port SRAM design - chip plan and array configuration Doug Sheppard |
| title_short | Dual port SRAM design - chip plan and array configuration |
| title_sort | dual port sram design chip plan and array configuration |
| topic | Random access memory Computer architecture Configuration management Logic design |
| topic_facet | Random access memory Computer architecture Configuration management Logic design Film |
| work_keys_str_mv | AT shepparddoug dualportsramdesignchipplanandarrayconfiguration AT shepparddoug dualportstaticrandomaccessmemorydesignchipplanandarrayconfiguration |