SRAM design - sensing and write control:
Course content reaffirmed: 06/2015--This tutorial completes the design of the control circuits and focuses on controlling the Sense Amp and enabling the write data. An additional requirement for decoding which columns are written to and read from will be achieved through column decode circuitry that...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch Video |
| Sprache: | English |
| Veröffentlicht: |
United States
IEEE
2010
|
| Schlagworte: | |
| Online-Zugang: | FHN01 TUM01 |
| Zusammenfassung: | Course content reaffirmed: 06/2015--This tutorial completes the design of the control circuits and focuses on controlling the Sense Amp and enabling the write data. An additional requirement for decoding which columns are written to and read from will be achieved through column decode circuitry that determines which SACL(3:0) and WCRWT(3:0) will be selected. One of the key features of the design will focus on Bit Line Ref (BLRF) which indicates when acceptable differential has been created at the input to the Sense Amp. This indicator is designed to tract the actual memory cell's driving of the bit lines in a way that can adjust the timing of SACL based on variations in process, conditions and changes in the drive strength of the accessed memory cell |
| Beschreibung: | Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020) |
| Beschreibung: | 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations |
| ISBN: | 9781424461943 |
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Datensatz im Suchindex
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| spelling | Sheppard, Doug Verfasser aut SRAM design - sensing and write control Doug Sheppard Static random-access memory design - sensing and write control United States IEEE 2010 1 Online-Resource (1 Videodatei, 60 Minuten) color illustrations tdi rdacontent c rdamedia cr rdacarrier Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 13, 2020) Course content reaffirmed: 06/2015--This tutorial completes the design of the control circuits and focuses on controlling the Sense Amp and enabling the write data. An additional requirement for decoding which columns are written to and read from will be achieved through column decode circuitry that determines which SACL(3:0) and WCRWT(3:0) will be selected. One of the key features of the design will focus on Bit Line Ref (BLRF) which indicates when acceptable differential has been created at the input to the Sense Amp. This indicator is designed to tract the actual memory cell's driving of the bit lines in a way that can adjust the timing of SACL based on variations in process, conditions and changes in the drive strength of the accessed memory cell Integrated circuits Random access memory Data processing Signal processing (DE-588)4017102-4 Film gnd-content |
| spellingShingle | Sheppard, Doug SRAM design - sensing and write control Integrated circuits Random access memory Data processing Signal processing |
| subject_GND | (DE-588)4017102-4 |
| title | SRAM design - sensing and write control |
| title_alt | Static random-access memory design - sensing and write control |
| title_auth | SRAM design - sensing and write control |
| title_exact_search | SRAM design - sensing and write control |
| title_exact_search_txtP | SRAM design - sensing and write control |
| title_full | SRAM design - sensing and write control Doug Sheppard |
| title_fullStr | SRAM design - sensing and write control Doug Sheppard |
| title_full_unstemmed | SRAM design - sensing and write control Doug Sheppard |
| title_short | SRAM design - sensing and write control |
| title_sort | sram design sensing and write control |
| topic | Integrated circuits Random access memory Data processing Signal processing |
| topic_facet | Integrated circuits Random access memory Data processing Signal processing Film |
| work_keys_str_mv | AT shepparddoug sramdesignsensingandwritecontrol AT shepparddoug staticrandomaccessmemorydesignsensingandwritecontrol |