SRAM design - write path:
Course content reaffirmed: 06/2015--The overall data path of a memory can be divided into two paths - the read path and the write path. This tutorial focuses on the write path of an SRAM. The write path has some unique requirements that the read path does not have, although there are some similariti...
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| Main Author: | |
|---|---|
| Format: | Electronic Video |
| Language: | English |
| Published: |
United States
IEEE
2009
|
| Subjects: | |
| Online Access: | FHN01 TUM01 |
| Summary: | Course content reaffirmed: 06/2015--The overall data path of a memory can be divided into two paths - the read path and the write path. This tutorial focuses on the write path of an SRAM. The write path has some unique requirements that the read path does not have, although there are some similarities as well. This design will include: the internal decoding for a write, the data in buffer and key control circuits along with their timing relationships. The overall integration of the write and read path will be designed thereby making up the complete data path into and out of the memory cell. A complete set of plots are provided along with a SPICE netlist that is extracted from the layout |
| Item Description: | Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 12, 2020) |
| Physical Description: | 1 Online-Resource (1 Videodatei, 60 Minuten) |
| ISBN: | 9781424461349 |
Staff View
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV047477079 | ||
| 003 | DE-604 | ||
| 005 | 20220218 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 210921s2009 |||| o||u| ||||||eng d | ||
| 020 | |a 9781424461349 |9 978-1-4244-6134-9 | ||
| 035 | |a (ZDB-37-ICG)EDP117 | ||
| 035 | |a (OCoLC)1269394210 | ||
| 035 | |a (DE-599)BVBBV047477079 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91 |a DE-92 | ||
| 082 | 0 | |a 621.38173 |2 23 | |
| 100 | 1 | |a Sheppard, Doug |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a SRAM design - write path |c Doug Sheppard |
| 246 | 1 | 3 | |a Static random-access memory design - write path |
| 264 | 1 | |a United States |b IEEE |c 2009 | |
| 300 | |a 1 Online-Resource (1 Videodatei, 60 Minuten) | ||
| 336 | |b tdi |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 12, 2020) | ||
| 520 | |a Course content reaffirmed: 06/2015--The overall data path of a memory can be divided into two paths - the read path and the write path. This tutorial focuses on the write path of an SRAM. The write path has some unique requirements that the read path does not have, although there are some similarities as well. This design will include: the internal decoding for a write, the data in buffer and key control circuits along with their timing relationships. The overall integration of the write and read path will be designed thereby making up the complete data path into and out of the memory cell. A complete set of plots are provided along with a SPICE netlist that is extracted from the layout | ||
| 650 | 4 | |a Integrated circuits | |
| 650 | 4 | |a Random access memory | |
| 655 | 7 | |0 (DE-588)4017102-4 |a Film |2 gnd-content | |
| 912 | |a ZDB-37-ICG | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-032878640 | ||
| 966 | e | |u https://ieeexplore.ieee.org/courses/details/EDP117 |l FHN01 |p ZDB-37-ICG |x Verlag |3 Volltext | |
| 966 | e | |u https://ieeexplore.ieee.org/courses/details/EDP117 |l TUM01 |p ZDB-37-ICG |x Verlag |3 Volltext | |
Record in the Search Index
| _version_ | 1804182793031254016 |
|---|---|
| adam_txt | |
| any_adam_object | |
| any_adam_object_boolean | |
| author | Sheppard, Doug |
| author_facet | Sheppard, Doug |
| author_role | aut |
| author_sort | Sheppard, Doug |
| author_variant | d s ds |
| building | Verbundindex |
| bvnumber | BV047477079 |
| collection | ZDB-37-ICG |
| ctrlnum | (ZDB-37-ICG)EDP117 (OCoLC)1269394210 (DE-599)BVBBV047477079 |
| dewey-full | 621.38173 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.38173 |
| dewey-search | 621.38173 |
| dewey-sort | 3621.38173 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic Video |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02068nmm a2200385zc 4500</leader><controlfield tag="001">BV047477079</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20220218 </controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">210921s2009 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781424461349</subfield><subfield code="9">978-1-4244-6134-9</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-37-ICG)EDP117</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1269394210</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV047477079</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91</subfield><subfield code="a">DE-92</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.38173</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Sheppard, Doug</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">SRAM design - write path</subfield><subfield code="c">Doug Sheppard</subfield></datafield><datafield tag="246" ind1="1" ind2="3"><subfield code="a">Static random-access memory design - write path</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">United States</subfield><subfield code="b">IEEE</subfield><subfield code="c">2009</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Resource (1 Videodatei, 60 Minuten)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">tdi</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 12, 2020)</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Course content reaffirmed: 06/2015--The overall data path of a memory can be divided into two paths - the read path and the write path. This tutorial focuses on the write path of an SRAM. The write path has some unique requirements that the read path does not have, although there are some similarities as well. This design will include: the internal decoding for a write, the data in buffer and key control circuits along with their timing relationships. The overall integration of the write and read path will be designed thereby making up the complete data path into and out of the memory cell. A complete set of plots are provided along with a SPICE netlist that is extracted from the layout</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Random access memory</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)4017102-4</subfield><subfield code="a">Film</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-37-ICG</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-032878640</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://ieeexplore.ieee.org/courses/details/EDP117</subfield><subfield code="l">FHN01</subfield><subfield code="p">ZDB-37-ICG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://ieeexplore.ieee.org/courses/details/EDP117</subfield><subfield code="l">TUM01</subfield><subfield code="p">ZDB-37-ICG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| genre | (DE-588)4017102-4 Film gnd-content |
| genre_facet | Film |
| id | DE-604.BV047477079 |
| illustrated | Not Illustrated |
| index_date | 2024-07-03T18:11:31Z |
| indexdate | 2024-07-10T09:13:11Z |
| institution | BVB |
| isbn | 9781424461349 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-032878640 |
| oclc_num | 1269394210 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-92 |
| owner_facet | DE-91 DE-BY-TUM DE-92 |
| physical | 1 Online-Resource (1 Videodatei, 60 Minuten) |
| psigel | ZDB-37-ICG |
| publishDate | 2009 |
| publishDateSearch | 2009 |
| publishDateSort | 2009 |
| publisher | IEEE |
| record_format | marc |
| spelling | Sheppard, Doug Verfasser aut SRAM design - write path Doug Sheppard Static random-access memory design - write path United States IEEE 2009 1 Online-Resource (1 Videodatei, 60 Minuten) tdi rdacontent c rdamedia cr rdacarrier Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 12, 2020) Course content reaffirmed: 06/2015--The overall data path of a memory can be divided into two paths - the read path and the write path. This tutorial focuses on the write path of an SRAM. The write path has some unique requirements that the read path does not have, although there are some similarities as well. This design will include: the internal decoding for a write, the data in buffer and key control circuits along with their timing relationships. The overall integration of the write and read path will be designed thereby making up the complete data path into and out of the memory cell. A complete set of plots are provided along with a SPICE netlist that is extracted from the layout Integrated circuits Random access memory (DE-588)4017102-4 Film gnd-content |
| spellingShingle | Sheppard, Doug SRAM design - write path Integrated circuits Random access memory |
| subject_GND | (DE-588)4017102-4 |
| title | SRAM design - write path |
| title_alt | Static random-access memory design - write path |
| title_auth | SRAM design - write path |
| title_exact_search | SRAM design - write path |
| title_exact_search_txtP | SRAM design - write path |
| title_full | SRAM design - write path Doug Sheppard |
| title_fullStr | SRAM design - write path Doug Sheppard |
| title_full_unstemmed | SRAM design - write path Doug Sheppard |
| title_short | SRAM design - write path |
| title_sort | sram design write path |
| topic | Integrated circuits Random access memory |
| topic_facet | Integrated circuits Random access memory Film |
| work_keys_str_mv | AT shepparddoug sramdesignwritepath AT shepparddoug staticrandomaccessmemorydesignwritepath |