SRAM design - array design and precharge:
Course content reaffirmed: 06/2015--A chip plan of the layout will be created from the architecture and block diagram discussed in the previous tutorial. This chip plan leads to the next design steps of the array and the circuits that interface to it. A very accurate model of the memory array will b...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch Video |
| Sprache: | English |
| Veröffentlicht: |
United States
IEEE
2009
|
| Schlagworte: | |
| Online-Zugang: | FHN01 TUM01 |
| Zusammenfassung: | Course content reaffirmed: 06/2015--A chip plan of the layout will be created from the architecture and block diagram discussed in the previous tutorial. This chip plan leads to the next design steps of the array and the circuits that interface to it. A very accurate model of the memory array will be developed and put into SPICE for all of the future simulations. Array waveforms from actual SPICE simulations will be reviewed in detail with a focus on the precharge signal and the resulting precharge circuitry that must interface to the bitlines. Schematics of the precharge circuit will be presented along with a detailed discussion of the requirements and how it relates to the read cycle. Layout of the precharge circuit will be supplied along with a SPICE netlist that includes extracted parasitic capacitance from the layout. Suggested order for proceeding through the IEEE eLearning Series on Design of Integrated Circuits tutorials: 1. Integrated Circuit Digital Design Methodology; 2. Integrated Circuit Digital Design Methodology - Advanced Analysis and Simulation; 3. SRAM Design - Overview and Memory Cell Division; 4. SRAM Design - Array Design and Precharge; 5. SRAM Design - Sensing Scheme; 6. SRAM Design - MUX Factor and Data Buffer; 7. SRAM Design - Write Path; 8. SRAM Design - ROW Decoder; 9. SRAM Design - Address Buffer; 10. SRAM Design - Clock Buffer; 11. SRAM Design - Control Circuitry; 12. SRAM Design - Sensing and Write Control |
| Beschreibung: | Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 10, 2020) |
| Beschreibung: | 1 Online-Resource (1 Videodatei, 60 Minuten) |
| ISBN: | 9781424430055 |
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| isbn | 9781424430055 |
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| spelling | Sheppard, Doug Verfasser aut SRAM design - array design and precharge Doug Sheppard Static random-access memory design - array design and precharge United States IEEE 2009 1 Online-Resource (1 Videodatei, 60 Minuten) tdi rdacontent c rdamedia cr rdacarrier Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 10, 2020) Course content reaffirmed: 06/2015--A chip plan of the layout will be created from the architecture and block diagram discussed in the previous tutorial. This chip plan leads to the next design steps of the array and the circuits that interface to it. A very accurate model of the memory array will be developed and put into SPICE for all of the future simulations. Array waveforms from actual SPICE simulations will be reviewed in detail with a focus on the precharge signal and the resulting precharge circuitry that must interface to the bitlines. Schematics of the precharge circuit will be presented along with a detailed discussion of the requirements and how it relates to the read cycle. Layout of the precharge circuit will be supplied along with a SPICE netlist that includes extracted parasitic capacitance from the layout. Suggested order for proceeding through the IEEE eLearning Series on Design of Integrated Circuits tutorials: 1. Integrated Circuit Digital Design Methodology; 2. Integrated Circuit Digital Design Methodology - Advanced Analysis and Simulation; 3. SRAM Design - Overview and Memory Cell Division; 4. SRAM Design - Array Design and Precharge; 5. SRAM Design - Sensing Scheme; 6. SRAM Design - MUX Factor and Data Buffer; 7. SRAM Design - Write Path; 8. SRAM Design - ROW Decoder; 9. SRAM Design - Address Buffer; 10. SRAM Design - Clock Buffer; 11. SRAM Design - Control Circuitry; 12. SRAM Design - Sensing and Write Control Integrated circuits Simulation Random access memory Data processing Computer architecture Signal processing (DE-588)4017102-4 Film gnd-content |
| spellingShingle | Sheppard, Doug SRAM design - array design and precharge Integrated circuits Simulation Random access memory Data processing Computer architecture Signal processing |
| subject_GND | (DE-588)4017102-4 |
| title | SRAM design - array design and precharge |
| title_alt | Static random-access memory design - array design and precharge |
| title_auth | SRAM design - array design and precharge |
| title_exact_search | SRAM design - array design and precharge |
| title_exact_search_txtP | SRAM design - array design and precharge |
| title_full | SRAM design - array design and precharge Doug Sheppard |
| title_fullStr | SRAM design - array design and precharge Doug Sheppard |
| title_full_unstemmed | SRAM design - array design and precharge Doug Sheppard |
| title_short | SRAM design - array design and precharge |
| title_sort | sram design array design and precharge |
| topic | Integrated circuits Simulation Random access memory Data processing Computer architecture Signal processing |
| topic_facet | Integrated circuits Simulation Random access memory Data processing Computer architecture Signal processing Film |
| work_keys_str_mv | AT shepparddoug sramdesignarraydesignandprecharge AT shepparddoug staticrandomaccessmemorydesignarraydesignandprecharge |