Course content reaffirmed: 06/2015--This tutorial walks you through the initial steps in designing an SRAM and then focuses on the first circuit that we must design - the memory cell. An overview of the architecture will be presented in a block diagram that will describe the functions of the major b...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	Sheppard, Doug (VerfasserIn)
Format:	Elektronisch Video
Sprache:	English
Veröffentlicht:	United States IEEE 2009
Schlagworte:	Integrated circuits Random access memory Film
Online-Zugang:	FHN01 TUM01
Zusammenfassung:	Course content reaffirmed: 06/2015--This tutorial walks you through the initial steps in designing an SRAM and then focuses on the first circuit that we must design - the memory cell. An overview of the architecture will be presented in a block diagram that will describe the functions of the major blocks required to create an SRAM. A large portion of this video will be dedicated to the design and layout of the memory cell (also called the bit cell) and how it is arrayed. It starts with a description of how the memory cell works then analyzes how the cell is read and written, with specific attention paid to read disturb which can cause the cell to inadvertently flip when it is read. Waveforms from SPICE simulations of the memory cell will be presented along with a SPICE input file that can be used to create your own simulations. A SPICE netlist from the layout of the memory cell will also be supplied so that the actual parasitic capacitance can be included in the simulations. Suggested order for proceeding through the IEEE eLearning Series on Design of Integrated Circuits tutorials: 1. Integrated Circuit Digital Design Methodology; 2. Integrated Circuit Digital Design Methodology - Advanced Analysis and Simulation; 3. SRAM Design - Overview and Memory Cell Division; 4. SRAM Design - Array Design and Precharge; 5. SRAM Design - Sensing Scheme; 6. SRAM Design - MUX Factor and Data Buffer; 7. SRAM Design - Write Path; 8. SRAM Design - ROW Decoder; 9. SRAM Design - Address Buffer; 10. SRAM Design - Clock Buffer; 11. SRAM Design - Control Circuitry; 12. SRAM Design - Sensing and Write Control
Beschreibung:	Description based on online resource; title from title screen (IEEE Xplore Digital Library, viewed November 10, 2020)
Beschreibung:	1 Online-Resource (1 Videodatei, 60 Minuten)
ISBN:	9781424430048