Definitive guide to ARM Cortex-M23 and Cortex-M33 processors:
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Elektronisch E-Book |
| Sprache: | English |
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Kidlington, Oxford, United Kingdom ; Cambridge, MA, United States
Newnes, an imprint of Elsevier
2021
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| Schlagworte: | |
| Online-Zugang: | TUM01 |
| Beschreibung: | Description based on publisher supplied metadata and other sources |
| Beschreibung: | 1 Online-Ressource Illustrationen, Diagramme |
| ISBN: | 9780128207369 |
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| 245 | 1 | 0 | |a Definitive guide to ARM Cortex-M23 and Cortex-M33 processors |c Joseph Yiu |
| 264 | 1 | |a Kidlington, Oxford, United Kingdom ; Cambridge, MA, United States |b Newnes, an imprint of Elsevier |c 2021 | |
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| 505 | 8 | |a Intro -- Definitive Guide to Arm Cortex-M23 and Cortex-M33 Processors -- Copyright -- Dedication -- Contents -- Preface -- Contributing author: Paul Beckmann -- Acknowledgments -- Chapter 1: Introduction -- 1.1. Microcontrollers and processors -- 1.2. Classification of processors -- 1.3. The Cortex-M23 and Cortex-M33 processors and the Armv8-M architecture -- 1.4. Characteristics of the Cortex-M23 and Cortex-M33 processors -- 1.5. Why have two different processors? -- 1.6. Applications of the Cortex-M23 and Cortex-M33 -- 1.7. Technical features -- 1.8. Comparison with previous generations of Cortex-M processors -- 1.9. Advantages of the Cortex-M23 and Cortex-M33 processors -- 1.10. Understanding microcontroller programming -- 1.11. Further reading -- 1.11.1. Product pages on developer.arm.com -- 1.11.2. Documentation on developer.arm.com -- 1.11.3. Community.arm.com -- References -- Chapter 2: Getting started with Cortex-M programming -- 2.1. Overview -- 2.1.1. Development suites -- 2.1.2. Development board -- 2.1.3. Debug adaptor -- 2.1.4. Resources -- 2.2. Some basic concepts -- 2.2.1. Reset -- 2.2.2. Clocks -- 2.2.3. Voltage level -- 2.2.4. Inputs and outputs -- 2.2.5. Introduction to embedded software program flows -- 2.2.5.1. Polling method -- 2.2.5.2. Interrupt driven method -- 2.2.5.3. Combination of polling and interrupt-driven methods -- 2.2.5.4. Handling concurrent processes -- 2.3. Introduction to Arm Cortex-M programming -- 2.3.1. C Programming-Data types -- 2.3.2. Accessing peripherals in C -- 2.3.3. What is inside a program image? -- 2.3.3.1. Vector table -- 2.3.3.2. Reset handler/startup code -- 2.3.3.3. C startup code -- 2.3.3.4. Application code -- 2.3.3.5. C library code -- 2.3.3.6. Other data -- 2.3.4. Data in SRAM -- 2.3.5. What happens when a microcontroller starts? -- 2.3.6. Understanding your hardware platform | |
| 505 | 8 | |a 2.4. Software development flow -- 2.5. Cortex Microcontroller Software Interface Standard (CMSIS) -- 2.5.1. Introduction of CMSIS -- 2.5.2. What is standardized in the CMSIS-CORE? -- 2.5.3. Using CMSIS-CORE -- 2.5.4. Benefits of CMSIS -- 2.6. Additional information on software development -- Reference -- Chapter 3: Technical overview of the Cortex-M23 and Cortex-M33 processors -- 3.1. Design objectives of Cortex-M23 and Cortex-M33 processors -- 3.2. Block diagrams -- 3.2.1. Cortex-M23 -- 3.2.2. Cortex-M33 -- 3.3. Processor -- 3.4. Instruction set -- 3.5. Memory map -- 3.6. Bus interfaces -- 3.7. Memory protection -- 3.8. Interrupt and exception handling -- 3.9. Low power features -- 3.10. OS support features -- 3.11. Floating-point unit -- 3.12. Coprocessor interface and Arm Custom Instructions -- 3.13. Debug and trace support -- 3.14. Multicore system design support -- 3.15. Key feature enhancements in Cortex-M23 and Cortex-M33 processors -- 3.15.1. Comparison between Cortex-M0+ and Cortex-M23 processors -- 3.15.2. Comparison between Cortex-M3/M4 and Cortex-M33 processors -- 3.16. Compatibility with other Cortex-M processors -- 3.17. Processor configuration options -- 3.18. Introduction to TrustZone -- 3.18.1. Overview of security requirements -- 3.18.2. Evolution of security in embedded systems -- 3.18.3. TrustZone for Armv8-M -- 3.19. Why TrustZone enables better security? -- 3.20. Firmware asset protection with eXecute-Only-Memory (XOM) -- Reference -- Chapter 4: Architecture -- 4.1. Introduction to the Armv8-M architecture -- 4.1.1. Overview -- 4.1.2. Background to the Armv8-M architecture -- 4.2. Programmer's model -- 4.2.1. Processor modes and states -- 4.2.2. Registers -- 4.2.2.1. Various types of registers -- 4.2.2.2. Registers in the register bank -- 4.2.2.3. Special registers -- Program Status Register (PSR) -- Interrupt masking registers | |
| 505 | 8 | |a CONTROL register -- Stack limit registers -- 4.2.2.4. Floating-point registers in Cortex-M33 -- 4.2.3. Behaviors of the APSR (ALU status flags) -- 4.2.3.1. Integer status flags -- 4.2.3.2. Q status flag -- 4.2.3.3. GE bits -- 4.2.4. Impact of TrustZone on the programmer's model -- 4.3. Memory system -- 4.3.1. Memory map -- 4.3.2. Partitioning of address spaces within TrustZone -- 4.3.3. System control space (SCS) and system control block (SCB) -- 4.3.4. Stack memory -- 4.3.5. Setting up and accessing of stack pointers and stack limit registers -- 4.3.6. Memory protection unit (MPU) -- 4.4. Exceptions and Interrupts -- 4.4.1. What are exceptions -- 4.4.2. TrustZone and exceptions -- 4.4.3. Nested Vectored Interrupt Controller (NVIC) -- 4.4.3.1. Flexible exception and interrupt management -- 4.4.3.2. Nested exception/interrupt support -- 4.4.3.3. Vectored exception/interrupt entry -- 4.4.3.4. Interrupt masking -- 4.4.4. Interrupt management with CMSIS-CORE -- 4.4.5. Vector tables -- 4.4.6. Fault handling -- 4.5. Debug -- 4.6. Reset and reset sequence -- 4.7. Other related architecture information -- References -- Chapter 5: Instruction set -- 5.1. Background -- 5.1.1. About this chapter -- 5.1.2. Background to the Instruction set in Arm Cortex-M processors -- 5.2. Instruction set features in various Cortex-M processors -- 5.3. Understanding the assembly language syntax -- 5.4. Use of a suffix in an instruction -- 5.5. Unified Assembly Language (UAL) -- 5.6. Instruction set-Moving data within the processors -- 5.6.1. Overview -- 5.6.2. Moving data between registers -- 5.6.3. Immediate data generation -- 5.6.4. Special register access instructions -- 5.6.5. Floating point register access -- 5.6.6. Floating point immediate data generation -- 5.6.7. Moving data between a register and a coprocessor register -- 5.7. Instruction set-Memory access | |
| 505 | 8 | |a 5.7.1. Overview -- 5.7.2. Single memory access -- 5.7.3. SP relative load/stores -- 5.7.4. Preindexed and postindex addressing modes -- 5.7.5. Optional shift in register offset (Barrel shifter) -- 5.7.6. Literal data read -- 5.7.7. Multiple load/store -- 5.7.8. PUSH/POP -- 5.7.9. Unprivileged access instructions -- 5.7.10. FPU memory access instructions -- 5.7.11. Exclusive access -- 5.7.12. Load acquire-store release -- 5.8. Instruction set-Arithmetic operations -- 5.9. Instruction set-Logic operations -- 5.10. Instruction set-Shift and rotate operations -- 5.11. Instruction set-Data conversions (extend and reverse ordering) -- 5.12. Instruction set-Bit field processing -- 5.13. Instruction set-Saturation operations -- 5.14. Instruction set-Program flow control -- 5.14.1. Overview -- 5.14.2. Branch -- 5.14.3. Function call -- 5.14.4. Conditional branch -- 5.14.5. Compare and branches (CBZ, CBNZ) -- 5.14.6. Conditional execution (IF-THEN instruction block) -- 5.14.7. Table branches (TBB and TBH) -- 5.15. Instruction set-DSP extension -- 5.15.1. Overview -- 5.15.2. SIMD concept -- 5.15.3. SIMD and saturating arithmetic instructions -- 5.15.4. Multiply and MAC instructions -- 5.15.5. Packing and unpacking instructions -- 5.16. Instruction set-Floating point support instructions -- 5.16.1. Overview of floating-point support in Armv8-M processors -- 5.16.2. Enabling the FPU -- 5.16.3. Floating point instructions -- 5.17. Instruction set-Exception-related instructions -- 5.18. Instruction set-Sleep mode-related instructions -- 5.19. Instruction set-Memory barrier instructions -- 5.20. Instruction set-TrustZone support instructions -- 5.21. Instruction set-Coprocessor and Arm custom instructions support -- 5.22. Instruction set-Other functions -- 5.23. Accessing special registers with the CMSIS-CORE -- References -- Chapter 6: Memory system | |
| 505 | 8 | |a 6.1. Overview of the memory system -- 6.1.1. What is in the memory system? -- 6.1.2. Memory system features -- 6.1.3. Key changes for the Cortex-M23/M33 when compared to the previous Cortex-M processors -- 6.2. Memory map -- 6.3. Memory types and memory attributes -- 6.3.1. Memory type classifications -- 6.3.2. Memory attributes overview -- 6.3.3. Memory attributes of the default memory map -- 6.4. Access permission management -- 6.4.1. Overview of access permission management -- 6.4.2. Access control mechanisms -- 6.4.3. Differences between the SAU/IDAU and the MPU -- 6.4.4. Default access permission -- 6.5. Memory endianness -- 6.6. Data alignment and unaligned data access support -- 6.7. Exclusive access support -- 6.8. Memory ordering and memory barrier instructions -- 6.9. Bus wait state and error support -- 6.10. Single-cycle I/O port-Cortex-M23 only -- 6.11. Memory systems in microcontrollers -- 6.11.1. Memory requirements -- 6.11.2. Bus system designs -- 6.11.3. Security management -- 6.12. Software considerations -- 6.12.1. Bus level power management -- 6.12.2. TrustZone security -- 6.12.3. Use of multiple load and store instructions -- References -- Chapter 7: TrustZone support in the memory system -- 7.1. Overview -- 7.1.1. About this chapter -- 7.1.2. Memory security attributes -- 7.2. SAU and IDAU -- 7.3. Banked and nonbanked registers -- 7.3.1. Overview -- 7.3.2. System Control Space (SCS) NS alias -- 7.4. Test Target (TT) instructions and region ID numbers -- 7.4.1. Why are the TT instructions needed? -- 7.4.2. The TT instructions -- 7.4.3. Region ID numbers -- 7.5. Memory protection controller and peripheral protection controller -- 7.6. Security aware peripherals -- References -- Chapter 8: Exceptions and interrupts-Architecture overview -- 8.1. Overview of exceptions and interrupts -- 8.1.1. The need for exceptions and interrupts | |
| 505 | 8 | |a 8.1.2. Basic concepts of peripheral interrupt operations | |
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| contents | Intro -- Definitive Guide to Arm Cortex-M23 and Cortex-M33 Processors -- Copyright -- Dedication -- Contents -- Preface -- Contributing author: Paul Beckmann -- Acknowledgments -- Chapter 1: Introduction -- 1.1. Microcontrollers and processors -- 1.2. Classification of processors -- 1.3. The Cortex-M23 and Cortex-M33 processors and the Armv8-M architecture -- 1.4. Characteristics of the Cortex-M23 and Cortex-M33 processors -- 1.5. Why have two different processors? -- 1.6. Applications of the Cortex-M23 and Cortex-M33 -- 1.7. Technical features -- 1.8. Comparison with previous generations of Cortex-M processors -- 1.9. Advantages of the Cortex-M23 and Cortex-M33 processors -- 1.10. Understanding microcontroller programming -- 1.11. Further reading -- 1.11.1. Product pages on developer.arm.com -- 1.11.2. Documentation on developer.arm.com -- 1.11.3. Community.arm.com -- References -- Chapter 2: Getting started with Cortex-M programming -- 2.1. Overview -- 2.1.1. Development suites -- 2.1.2. Development board -- 2.1.3. Debug adaptor -- 2.1.4. Resources -- 2.2. Some basic concepts -- 2.2.1. Reset -- 2.2.2. Clocks -- 2.2.3. Voltage level -- 2.2.4. Inputs and outputs -- 2.2.5. Introduction to embedded software program flows -- 2.2.5.1. Polling method -- 2.2.5.2. Interrupt driven method -- 2.2.5.3. Combination of polling and interrupt-driven methods -- 2.2.5.4. Handling concurrent processes -- 2.3. Introduction to Arm Cortex-M programming -- 2.3.1. C Programming-Data types -- 2.3.2. Accessing peripherals in C -- 2.3.3. What is inside a program image? -- 2.3.3.1. Vector table -- 2.3.3.2. Reset handler/startup code -- 2.3.3.3. C startup code -- 2.3.3.4. Application code -- 2.3.3.5. C library code -- 2.3.3.6. Other data -- 2.3.4. Data in SRAM -- 2.3.5. What happens when a microcontroller starts? -- 2.3.6. Understanding your hardware platform 2.4. Software development flow -- 2.5. Cortex Microcontroller Software Interface Standard (CMSIS) -- 2.5.1. Introduction of CMSIS -- 2.5.2. What is standardized in the CMSIS-CORE? -- 2.5.3. Using CMSIS-CORE -- 2.5.4. Benefits of CMSIS -- 2.6. Additional information on software development -- Reference -- Chapter 3: Technical overview of the Cortex-M23 and Cortex-M33 processors -- 3.1. Design objectives of Cortex-M23 and Cortex-M33 processors -- 3.2. Block diagrams -- 3.2.1. Cortex-M23 -- 3.2.2. Cortex-M33 -- 3.3. Processor -- 3.4. Instruction set -- 3.5. Memory map -- 3.6. Bus interfaces -- 3.7. Memory protection -- 3.8. Interrupt and exception handling -- 3.9. Low power features -- 3.10. OS support features -- 3.11. Floating-point unit -- 3.12. Coprocessor interface and Arm Custom Instructions -- 3.13. Debug and trace support -- 3.14. Multicore system design support -- 3.15. Key feature enhancements in Cortex-M23 and Cortex-M33 processors -- 3.15.1. Comparison between Cortex-M0+ and Cortex-M23 processors -- 3.15.2. Comparison between Cortex-M3/M4 and Cortex-M33 processors -- 3.16. Compatibility with other Cortex-M processors -- 3.17. Processor configuration options -- 3.18. Introduction to TrustZone -- 3.18.1. Overview of security requirements -- 3.18.2. Evolution of security in embedded systems -- 3.18.3. TrustZone for Armv8-M -- 3.19. Why TrustZone enables better security? -- 3.20. Firmware asset protection with eXecute-Only-Memory (XOM) -- Reference -- Chapter 4: Architecture -- 4.1. Introduction to the Armv8-M architecture -- 4.1.1. Overview -- 4.1.2. Background to the Armv8-M architecture -- 4.2. Programmer's model -- 4.2.1. Processor modes and states -- 4.2.2. Registers -- 4.2.2.1. Various types of registers -- 4.2.2.2. Registers in the register bank -- 4.2.2.3. Special registers -- Program Status Register (PSR) -- Interrupt masking registers CONTROL register -- Stack limit registers -- 4.2.2.4. Floating-point registers in Cortex-M33 -- 4.2.3. Behaviors of the APSR (ALU status flags) -- 4.2.3.1. Integer status flags -- 4.2.3.2. Q status flag -- 4.2.3.3. GE bits -- 4.2.4. Impact of TrustZone on the programmer's model -- 4.3. Memory system -- 4.3.1. Memory map -- 4.3.2. Partitioning of address spaces within TrustZone -- 4.3.3. System control space (SCS) and system control block (SCB) -- 4.3.4. Stack memory -- 4.3.5. Setting up and accessing of stack pointers and stack limit registers -- 4.3.6. Memory protection unit (MPU) -- 4.4. Exceptions and Interrupts -- 4.4.1. What are exceptions -- 4.4.2. TrustZone and exceptions -- 4.4.3. Nested Vectored Interrupt Controller (NVIC) -- 4.4.3.1. Flexible exception and interrupt management -- 4.4.3.2. Nested exception/interrupt support -- 4.4.3.3. Vectored exception/interrupt entry -- 4.4.3.4. Interrupt masking -- 4.4.4. Interrupt management with CMSIS-CORE -- 4.4.5. Vector tables -- 4.4.6. Fault handling -- 4.5. Debug -- 4.6. Reset and reset sequence -- 4.7. Other related architecture information -- References -- Chapter 5: Instruction set -- 5.1. Background -- 5.1.1. About this chapter -- 5.1.2. Background to the Instruction set in Arm Cortex-M processors -- 5.2. Instruction set features in various Cortex-M processors -- 5.3. Understanding the assembly language syntax -- 5.4. Use of a suffix in an instruction -- 5.5. Unified Assembly Language (UAL) -- 5.6. Instruction set-Moving data within the processors -- 5.6.1. Overview -- 5.6.2. Moving data between registers -- 5.6.3. Immediate data generation -- 5.6.4. Special register access instructions -- 5.6.5. Floating point register access -- 5.6.6. Floating point immediate data generation -- 5.6.7. Moving data between a register and a coprocessor register -- 5.7. Instruction set-Memory access 5.7.1. Overview -- 5.7.2. Single memory access -- 5.7.3. SP relative load/stores -- 5.7.4. Preindexed and postindex addressing modes -- 5.7.5. Optional shift in register offset (Barrel shifter) -- 5.7.6. Literal data read -- 5.7.7. Multiple load/store -- 5.7.8. PUSH/POP -- 5.7.9. Unprivileged access instructions -- 5.7.10. FPU memory access instructions -- 5.7.11. Exclusive access -- 5.7.12. Load acquire-store release -- 5.8. Instruction set-Arithmetic operations -- 5.9. Instruction set-Logic operations -- 5.10. Instruction set-Shift and rotate operations -- 5.11. Instruction set-Data conversions (extend and reverse ordering) -- 5.12. Instruction set-Bit field processing -- 5.13. Instruction set-Saturation operations -- 5.14. Instruction set-Program flow control -- 5.14.1. Overview -- 5.14.2. Branch -- 5.14.3. Function call -- 5.14.4. Conditional branch -- 5.14.5. Compare and branches (CBZ, CBNZ) -- 5.14.6. Conditional execution (IF-THEN instruction block) -- 5.14.7. Table branches (TBB and TBH) -- 5.15. Instruction set-DSP extension -- 5.15.1. Overview -- 5.15.2. SIMD concept -- 5.15.3. SIMD and saturating arithmetic instructions -- 5.15.4. Multiply and MAC instructions -- 5.15.5. Packing and unpacking instructions -- 5.16. Instruction set-Floating point support instructions -- 5.16.1. Overview of floating-point support in Armv8-M processors -- 5.16.2. Enabling the FPU -- 5.16.3. Floating point instructions -- 5.17. Instruction set-Exception-related instructions -- 5.18. Instruction set-Sleep mode-related instructions -- 5.19. Instruction set-Memory barrier instructions -- 5.20. Instruction set-TrustZone support instructions -- 5.21. Instruction set-Coprocessor and Arm custom instructions support -- 5.22. Instruction set-Other functions -- 5.23. Accessing special registers with the CMSIS-CORE -- References -- Chapter 6: Memory system 6.1. Overview of the memory system -- 6.1.1. What is in the memory system? -- 6.1.2. Memory system features -- 6.1.3. Key changes for the Cortex-M23/M33 when compared to the previous Cortex-M processors -- 6.2. Memory map -- 6.3. Memory types and memory attributes -- 6.3.1. Memory type classifications -- 6.3.2. Memory attributes overview -- 6.3.3. Memory attributes of the default memory map -- 6.4. Access permission management -- 6.4.1. Overview of access permission management -- 6.4.2. Access control mechanisms -- 6.4.3. Differences between the SAU/IDAU and the MPU -- 6.4.4. Default access permission -- 6.5. Memory endianness -- 6.6. Data alignment and unaligned data access support -- 6.7. Exclusive access support -- 6.8. Memory ordering and memory barrier instructions -- 6.9. Bus wait state and error support -- 6.10. Single-cycle I/O port-Cortex-M23 only -- 6.11. Memory systems in microcontrollers -- 6.11.1. Memory requirements -- 6.11.2. Bus system designs -- 6.11.3. Security management -- 6.12. Software considerations -- 6.12.1. Bus level power management -- 6.12.2. TrustZone security -- 6.12.3. Use of multiple load and store instructions -- References -- Chapter 7: TrustZone support in the memory system -- 7.1. Overview -- 7.1.1. About this chapter -- 7.1.2. Memory security attributes -- 7.2. SAU and IDAU -- 7.3. Banked and nonbanked registers -- 7.3.1. Overview -- 7.3.2. System Control Space (SCS) NS alias -- 7.4. Test Target (TT) instructions and region ID numbers -- 7.4.1. Why are the TT instructions needed? -- 7.4.2. The TT instructions -- 7.4.3. Region ID numbers -- 7.5. Memory protection controller and peripheral protection controller -- 7.6. Security aware peripherals -- References -- Chapter 8: Exceptions and interrupts-Architecture overview -- 8.1. Overview of exceptions and interrupts -- 8.1.1. The need for exceptions and interrupts 8.1.2. Basic concepts of peripheral interrupt operations |
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| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>11834nmm a2200625zc 4500</leader><controlfield tag="001">BV047442443</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20230728 </controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">210827s2021 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780128207369</subfield><subfield code="9">978-0-12-820736-9</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-30-PQE)EBC6419164</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-30-PAD)EBC6419164</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-89-EBL)EBL6419164</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1225543903</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV047442443</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">004.16</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 170</subfield><subfield code="0">(DE-625)143602:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 210</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Yiu, Joseph</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)13908665X</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Definitive guide to ARM Cortex-M23 and Cortex-M33 processors</subfield><subfield code="c">Joseph Yiu</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Kidlington, Oxford, United Kingdom ; Cambridge, MA, United States</subfield><subfield code="b">Newnes, an imprint of Elsevier</subfield><subfield code="c">2021</subfield></datafield><datafield tag="264" ind1=" " ind2="4"><subfield code="c">© 2021</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource</subfield><subfield code="b">Illustrationen, Diagramme</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Description based on publisher supplied metadata and other sources</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">Intro -- Definitive Guide to Arm Cortex-M23 and Cortex-M33 Processors -- Copyright -- Dedication -- Contents -- Preface -- Contributing author: Paul Beckmann -- Acknowledgments -- Chapter 1: Introduction -- 1.1. Microcontrollers and processors -- 1.2. Classification of processors -- 1.3. The Cortex-M23 and Cortex-M33 processors and the Armv8-M architecture -- 1.4. Characteristics of the Cortex-M23 and Cortex-M33 processors -- 1.5. Why have two different processors? -- 1.6. Applications of the Cortex-M23 and Cortex-M33 -- 1.7. Technical features -- 1.8. Comparison with previous generations of Cortex-M processors -- 1.9. Advantages of the Cortex-M23 and Cortex-M33 processors -- 1.10. Understanding microcontroller programming -- 1.11. Further reading -- 1.11.1. Product pages on developer.arm.com -- 1.11.2. Documentation on developer.arm.com -- 1.11.3. Community.arm.com -- References -- Chapter 2: Getting started with Cortex-M programming -- 2.1. Overview -- 2.1.1. Development suites -- 2.1.2. Development board -- 2.1.3. Debug adaptor -- 2.1.4. Resources -- 2.2. Some basic concepts -- 2.2.1. Reset -- 2.2.2. Clocks -- 2.2.3. Voltage level -- 2.2.4. Inputs and outputs -- 2.2.5. Introduction to embedded software program flows -- 2.2.5.1. Polling method -- 2.2.5.2. Interrupt driven method -- 2.2.5.3. Combination of polling and interrupt-driven methods -- 2.2.5.4. Handling concurrent processes -- 2.3. Introduction to Arm Cortex-M programming -- 2.3.1. C Programming-Data types -- 2.3.2. Accessing peripherals in C -- 2.3.3. What is inside a program image? -- 2.3.3.1. Vector table -- 2.3.3.2. Reset handler/startup code -- 2.3.3.3. C startup code -- 2.3.3.4. Application code -- 2.3.3.5. C library code -- 2.3.3.6. Other data -- 2.3.4. Data in SRAM -- 2.3.5. What happens when a microcontroller starts? -- 2.3.6. Understanding your hardware platform</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">2.4. Software development flow -- 2.5. Cortex Microcontroller Software Interface Standard (CMSIS) -- 2.5.1. Introduction of CMSIS -- 2.5.2. What is standardized in the CMSIS-CORE? -- 2.5.3. Using CMSIS-CORE -- 2.5.4. Benefits of CMSIS -- 2.6. Additional information on software development -- Reference -- Chapter 3: Technical overview of the Cortex-M23 and Cortex-M33 processors -- 3.1. Design objectives of Cortex-M23 and Cortex-M33 processors -- 3.2. Block diagrams -- 3.2.1. Cortex-M23 -- 3.2.2. Cortex-M33 -- 3.3. Processor -- 3.4. Instruction set -- 3.5. Memory map -- 3.6. Bus interfaces -- 3.7. Memory protection -- 3.8. Interrupt and exception handling -- 3.9. Low power features -- 3.10. OS support features -- 3.11. Floating-point unit -- 3.12. Coprocessor interface and Arm Custom Instructions -- 3.13. Debug and trace support -- 3.14. Multicore system design support -- 3.15. Key feature enhancements in Cortex-M23 and Cortex-M33 processors -- 3.15.1. Comparison between Cortex-M0+ and Cortex-M23 processors -- 3.15.2. Comparison between Cortex-M3/M4 and Cortex-M33 processors -- 3.16. Compatibility with other Cortex-M processors -- 3.17. Processor configuration options -- 3.18. Introduction to TrustZone -- 3.18.1. Overview of security requirements -- 3.18.2. Evolution of security in embedded systems -- 3.18.3. TrustZone for Armv8-M -- 3.19. Why TrustZone enables better security? -- 3.20. Firmware asset protection with eXecute-Only-Memory (XOM) -- Reference -- Chapter 4: Architecture -- 4.1. Introduction to the Armv8-M architecture -- 4.1.1. Overview -- 4.1.2. Background to the Armv8-M architecture -- 4.2. Programmer's model -- 4.2.1. Processor modes and states -- 4.2.2. Registers -- 4.2.2.1. Various types of registers -- 4.2.2.2. Registers in the register bank -- 4.2.2.3. Special registers -- Program Status Register (PSR) -- Interrupt masking registers</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">CONTROL register -- Stack limit registers -- 4.2.2.4. Floating-point registers in Cortex-M33 -- 4.2.3. Behaviors of the APSR (ALU status flags) -- 4.2.3.1. Integer status flags -- 4.2.3.2. Q status flag -- 4.2.3.3. GE bits -- 4.2.4. Impact of TrustZone on the programmer's model -- 4.3. Memory system -- 4.3.1. Memory map -- 4.3.2. Partitioning of address spaces within TrustZone -- 4.3.3. System control space (SCS) and system control block (SCB) -- 4.3.4. Stack memory -- 4.3.5. Setting up and accessing of stack pointers and stack limit registers -- 4.3.6. Memory protection unit (MPU) -- 4.4. Exceptions and Interrupts -- 4.4.1. What are exceptions -- 4.4.2. TrustZone and exceptions -- 4.4.3. Nested Vectored Interrupt Controller (NVIC) -- 4.4.3.1. Flexible exception and interrupt management -- 4.4.3.2. Nested exception/interrupt support -- 4.4.3.3. Vectored exception/interrupt entry -- 4.4.3.4. Interrupt masking -- 4.4.4. Interrupt management with CMSIS-CORE -- 4.4.5. Vector tables -- 4.4.6. Fault handling -- 4.5. Debug -- 4.6. Reset and reset sequence -- 4.7. Other related architecture information -- References -- Chapter 5: Instruction set -- 5.1. Background -- 5.1.1. About this chapter -- 5.1.2. Background to the Instruction set in Arm Cortex-M processors -- 5.2. Instruction set features in various Cortex-M processors -- 5.3. Understanding the assembly language syntax -- 5.4. Use of a suffix in an instruction -- 5.5. Unified Assembly Language (UAL) -- 5.6. Instruction set-Moving data within the processors -- 5.6.1. Overview -- 5.6.2. Moving data between registers -- 5.6.3. Immediate data generation -- 5.6.4. Special register access instructions -- 5.6.5. Floating point register access -- 5.6.6. Floating point immediate data generation -- 5.6.7. Moving data between a register and a coprocessor register -- 5.7. Instruction set-Memory access</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">5.7.1. Overview -- 5.7.2. Single memory access -- 5.7.3. SP relative load/stores -- 5.7.4. Preindexed and postindex addressing modes -- 5.7.5. Optional shift in register offset (Barrel shifter) -- 5.7.6. Literal data read -- 5.7.7. Multiple load/store -- 5.7.8. PUSH/POP -- 5.7.9. Unprivileged access instructions -- 5.7.10. FPU memory access instructions -- 5.7.11. Exclusive access -- 5.7.12. Load acquire-store release -- 5.8. Instruction set-Arithmetic operations -- 5.9. Instruction set-Logic operations -- 5.10. Instruction set-Shift and rotate operations -- 5.11. Instruction set-Data conversions (extend and reverse ordering) -- 5.12. Instruction set-Bit field processing -- 5.13. Instruction set-Saturation operations -- 5.14. Instruction set-Program flow control -- 5.14.1. Overview -- 5.14.2. Branch -- 5.14.3. Function call -- 5.14.4. Conditional branch -- 5.14.5. Compare and branches (CBZ, CBNZ) -- 5.14.6. Conditional execution (IF-THEN instruction block) -- 5.14.7. Table branches (TBB and TBH) -- 5.15. Instruction set-DSP extension -- 5.15.1. Overview -- 5.15.2. SIMD concept -- 5.15.3. SIMD and saturating arithmetic instructions -- 5.15.4. Multiply and MAC instructions -- 5.15.5. Packing and unpacking instructions -- 5.16. Instruction set-Floating point support instructions -- 5.16.1. Overview of floating-point support in Armv8-M processors -- 5.16.2. Enabling the FPU -- 5.16.3. Floating point instructions -- 5.17. Instruction set-Exception-related instructions -- 5.18. Instruction set-Sleep mode-related instructions -- 5.19. Instruction set-Memory barrier instructions -- 5.20. Instruction set-TrustZone support instructions -- 5.21. Instruction set-Coprocessor and Arm custom instructions support -- 5.22. Instruction set-Other functions -- 5.23. Accessing special registers with the CMSIS-CORE -- References -- Chapter 6: Memory system</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">6.1. Overview of the memory system -- 6.1.1. What is in the memory system? -- 6.1.2. Memory system features -- 6.1.3. Key changes for the Cortex-M23/M33 when compared to the previous Cortex-M processors -- 6.2. Memory map -- 6.3. Memory types and memory attributes -- 6.3.1. Memory type classifications -- 6.3.2. Memory attributes overview -- 6.3.3. Memory attributes of the default memory map -- 6.4. Access permission management -- 6.4.1. Overview of access permission management -- 6.4.2. Access control mechanisms -- 6.4.3. Differences between the SAU/IDAU and the MPU -- 6.4.4. Default access permission -- 6.5. Memory endianness -- 6.6. Data alignment and unaligned data access support -- 6.7. Exclusive access support -- 6.8. Memory ordering and memory barrier instructions -- 6.9. Bus wait state and error support -- 6.10. Single-cycle I/O port-Cortex-M23 only -- 6.11. Memory systems in microcontrollers -- 6.11.1. Memory requirements -- 6.11.2. Bus system designs -- 6.11.3. Security management -- 6.12. Software considerations -- 6.12.1. Bus level power management -- 6.12.2. TrustZone security -- 6.12.3. Use of multiple load and store instructions -- References -- Chapter 7: TrustZone support in the memory system -- 7.1. Overview -- 7.1.1. About this chapter -- 7.1.2. Memory security attributes -- 7.2. SAU and IDAU -- 7.3. Banked and nonbanked registers -- 7.3.1. Overview -- 7.3.2. System Control Space (SCS) NS alias -- 7.4. Test Target (TT) instructions and region ID numbers -- 7.4.1. Why are the TT instructions needed? -- 7.4.2. The TT instructions -- 7.4.3. Region ID numbers -- 7.5. Memory protection controller and peripheral protection controller -- 7.6. Security aware peripherals -- References -- Chapter 8: Exceptions and interrupts-Architecture overview -- 8.1. Overview of exceptions and interrupts -- 8.1.1. The need for exceptions and interrupts</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">8.1.2. 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| id | DE-604.BV047442443 |
| illustrated | Not Illustrated |
| index_date | 2024-07-03T18:01:24Z |
| indexdate | 2024-07-10T09:12:16Z |
| institution | BVB |
| isbn | 9780128207369 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-032844595 |
| oclc_num | 1225543903 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM |
| owner_facet | DE-91 DE-BY-TUM |
| physical | 1 Online-Ressource Illustrationen, Diagramme |
| psigel | ZDB-30-PQE ZDB-30-PQE TUM_PDA_PQE_Kauf |
| publishDate | 2021 |
| publishDateSearch | 2021 |
| publishDateSort | 2021 |
| publisher | Newnes, an imprint of Elsevier |
| record_format | marc |
| spelling | Yiu, Joseph Verfasser (DE-588)13908665X aut Definitive guide to ARM Cortex-M23 and Cortex-M33 processors Joseph Yiu Kidlington, Oxford, United Kingdom ; Cambridge, MA, United States Newnes, an imprint of Elsevier 2021 © 2021 1 Online-Ressource Illustrationen, Diagramme txt rdacontent c rdamedia cr rdacarrier Description based on publisher supplied metadata and other sources Intro -- Definitive Guide to Arm Cortex-M23 and Cortex-M33 Processors -- Copyright -- Dedication -- Contents -- Preface -- Contributing author: Paul Beckmann -- Acknowledgments -- Chapter 1: Introduction -- 1.1. Microcontrollers and processors -- 1.2. Classification of processors -- 1.3. The Cortex-M23 and Cortex-M33 processors and the Armv8-M architecture -- 1.4. Characteristics of the Cortex-M23 and Cortex-M33 processors -- 1.5. Why have two different processors? -- 1.6. Applications of the Cortex-M23 and Cortex-M33 -- 1.7. Technical features -- 1.8. Comparison with previous generations of Cortex-M processors -- 1.9. Advantages of the Cortex-M23 and Cortex-M33 processors -- 1.10. Understanding microcontroller programming -- 1.11. Further reading -- 1.11.1. Product pages on developer.arm.com -- 1.11.2. Documentation on developer.arm.com -- 1.11.3. Community.arm.com -- References -- Chapter 2: Getting started with Cortex-M programming -- 2.1. Overview -- 2.1.1. Development suites -- 2.1.2. Development board -- 2.1.3. Debug adaptor -- 2.1.4. Resources -- 2.2. Some basic concepts -- 2.2.1. Reset -- 2.2.2. Clocks -- 2.2.3. Voltage level -- 2.2.4. Inputs and outputs -- 2.2.5. Introduction to embedded software program flows -- 2.2.5.1. Polling method -- 2.2.5.2. Interrupt driven method -- 2.2.5.3. Combination of polling and interrupt-driven methods -- 2.2.5.4. Handling concurrent processes -- 2.3. Introduction to Arm Cortex-M programming -- 2.3.1. C Programming-Data types -- 2.3.2. Accessing peripherals in C -- 2.3.3. What is inside a program image? -- 2.3.3.1. Vector table -- 2.3.3.2. Reset handler/startup code -- 2.3.3.3. C startup code -- 2.3.3.4. Application code -- 2.3.3.5. C library code -- 2.3.3.6. Other data -- 2.3.4. Data in SRAM -- 2.3.5. What happens when a microcontroller starts? -- 2.3.6. Understanding your hardware platform 2.4. Software development flow -- 2.5. Cortex Microcontroller Software Interface Standard (CMSIS) -- 2.5.1. Introduction of CMSIS -- 2.5.2. What is standardized in the CMSIS-CORE? -- 2.5.3. Using CMSIS-CORE -- 2.5.4. Benefits of CMSIS -- 2.6. Additional information on software development -- Reference -- Chapter 3: Technical overview of the Cortex-M23 and Cortex-M33 processors -- 3.1. Design objectives of Cortex-M23 and Cortex-M33 processors -- 3.2. Block diagrams -- 3.2.1. Cortex-M23 -- 3.2.2. Cortex-M33 -- 3.3. Processor -- 3.4. Instruction set -- 3.5. Memory map -- 3.6. Bus interfaces -- 3.7. Memory protection -- 3.8. Interrupt and exception handling -- 3.9. Low power features -- 3.10. OS support features -- 3.11. Floating-point unit -- 3.12. Coprocessor interface and Arm Custom Instructions -- 3.13. Debug and trace support -- 3.14. Multicore system design support -- 3.15. Key feature enhancements in Cortex-M23 and Cortex-M33 processors -- 3.15.1. Comparison between Cortex-M0+ and Cortex-M23 processors -- 3.15.2. Comparison between Cortex-M3/M4 and Cortex-M33 processors -- 3.16. Compatibility with other Cortex-M processors -- 3.17. Processor configuration options -- 3.18. Introduction to TrustZone -- 3.18.1. Overview of security requirements -- 3.18.2. Evolution of security in embedded systems -- 3.18.3. TrustZone for Armv8-M -- 3.19. Why TrustZone enables better security? -- 3.20. Firmware asset protection with eXecute-Only-Memory (XOM) -- Reference -- Chapter 4: Architecture -- 4.1. Introduction to the Armv8-M architecture -- 4.1.1. Overview -- 4.1.2. Background to the Armv8-M architecture -- 4.2. Programmer's model -- 4.2.1. Processor modes and states -- 4.2.2. Registers -- 4.2.2.1. Various types of registers -- 4.2.2.2. Registers in the register bank -- 4.2.2.3. Special registers -- Program Status Register (PSR) -- Interrupt masking registers CONTROL register -- Stack limit registers -- 4.2.2.4. Floating-point registers in Cortex-M33 -- 4.2.3. Behaviors of the APSR (ALU status flags) -- 4.2.3.1. Integer status flags -- 4.2.3.2. Q status flag -- 4.2.3.3. GE bits -- 4.2.4. Impact of TrustZone on the programmer's model -- 4.3. Memory system -- 4.3.1. Memory map -- 4.3.2. Partitioning of address spaces within TrustZone -- 4.3.3. System control space (SCS) and system control block (SCB) -- 4.3.4. Stack memory -- 4.3.5. Setting up and accessing of stack pointers and stack limit registers -- 4.3.6. Memory protection unit (MPU) -- 4.4. Exceptions and Interrupts -- 4.4.1. What are exceptions -- 4.4.2. TrustZone and exceptions -- 4.4.3. Nested Vectored Interrupt Controller (NVIC) -- 4.4.3.1. Flexible exception and interrupt management -- 4.4.3.2. Nested exception/interrupt support -- 4.4.3.3. Vectored exception/interrupt entry -- 4.4.3.4. Interrupt masking -- 4.4.4. Interrupt management with CMSIS-CORE -- 4.4.5. Vector tables -- 4.4.6. Fault handling -- 4.5. Debug -- 4.6. Reset and reset sequence -- 4.7. Other related architecture information -- References -- Chapter 5: Instruction set -- 5.1. Background -- 5.1.1. About this chapter -- 5.1.2. Background to the Instruction set in Arm Cortex-M processors -- 5.2. Instruction set features in various Cortex-M processors -- 5.3. Understanding the assembly language syntax -- 5.4. Use of a suffix in an instruction -- 5.5. Unified Assembly Language (UAL) -- 5.6. Instruction set-Moving data within the processors -- 5.6.1. Overview -- 5.6.2. Moving data between registers -- 5.6.3. Immediate data generation -- 5.6.4. Special register access instructions -- 5.6.5. Floating point register access -- 5.6.6. Floating point immediate data generation -- 5.6.7. Moving data between a register and a coprocessor register -- 5.7. Instruction set-Memory access 5.7.1. Overview -- 5.7.2. Single memory access -- 5.7.3. SP relative load/stores -- 5.7.4. Preindexed and postindex addressing modes -- 5.7.5. Optional shift in register offset (Barrel shifter) -- 5.7.6. Literal data read -- 5.7.7. Multiple load/store -- 5.7.8. PUSH/POP -- 5.7.9. Unprivileged access instructions -- 5.7.10. FPU memory access instructions -- 5.7.11. Exclusive access -- 5.7.12. Load acquire-store release -- 5.8. Instruction set-Arithmetic operations -- 5.9. Instruction set-Logic operations -- 5.10. Instruction set-Shift and rotate operations -- 5.11. Instruction set-Data conversions (extend and reverse ordering) -- 5.12. Instruction set-Bit field processing -- 5.13. Instruction set-Saturation operations -- 5.14. Instruction set-Program flow control -- 5.14.1. Overview -- 5.14.2. Branch -- 5.14.3. Function call -- 5.14.4. Conditional branch -- 5.14.5. Compare and branches (CBZ, CBNZ) -- 5.14.6. Conditional execution (IF-THEN instruction block) -- 5.14.7. Table branches (TBB and TBH) -- 5.15. Instruction set-DSP extension -- 5.15.1. Overview -- 5.15.2. SIMD concept -- 5.15.3. SIMD and saturating arithmetic instructions -- 5.15.4. Multiply and MAC instructions -- 5.15.5. Packing and unpacking instructions -- 5.16. Instruction set-Floating point support instructions -- 5.16.1. Overview of floating-point support in Armv8-M processors -- 5.16.2. Enabling the FPU -- 5.16.3. Floating point instructions -- 5.17. Instruction set-Exception-related instructions -- 5.18. Instruction set-Sleep mode-related instructions -- 5.19. Instruction set-Memory barrier instructions -- 5.20. Instruction set-TrustZone support instructions -- 5.21. Instruction set-Coprocessor and Arm custom instructions support -- 5.22. Instruction set-Other functions -- 5.23. Accessing special registers with the CMSIS-CORE -- References -- Chapter 6: Memory system 6.1. Overview of the memory system -- 6.1.1. What is in the memory system? -- 6.1.2. Memory system features -- 6.1.3. Key changes for the Cortex-M23/M33 when compared to the previous Cortex-M processors -- 6.2. Memory map -- 6.3. Memory types and memory attributes -- 6.3.1. Memory type classifications -- 6.3.2. Memory attributes overview -- 6.3.3. Memory attributes of the default memory map -- 6.4. Access permission management -- 6.4.1. Overview of access permission management -- 6.4.2. Access control mechanisms -- 6.4.3. Differences between the SAU/IDAU and the MPU -- 6.4.4. Default access permission -- 6.5. Memory endianness -- 6.6. Data alignment and unaligned data access support -- 6.7. Exclusive access support -- 6.8. Memory ordering and memory barrier instructions -- 6.9. Bus wait state and error support -- 6.10. Single-cycle I/O port-Cortex-M23 only -- 6.11. Memory systems in microcontrollers -- 6.11.1. Memory requirements -- 6.11.2. Bus system designs -- 6.11.3. Security management -- 6.12. Software considerations -- 6.12.1. Bus level power management -- 6.12.2. TrustZone security -- 6.12.3. Use of multiple load and store instructions -- References -- Chapter 7: TrustZone support in the memory system -- 7.1. Overview -- 7.1.1. About this chapter -- 7.1.2. Memory security attributes -- 7.2. SAU and IDAU -- 7.3. Banked and nonbanked registers -- 7.3.1. Overview -- 7.3.2. System Control Space (SCS) NS alias -- 7.4. Test Target (TT) instructions and region ID numbers -- 7.4.1. Why are the TT instructions needed? -- 7.4.2. The TT instructions -- 7.4.3. Region ID numbers -- 7.5. Memory protection controller and peripheral protection controller -- 7.6. Security aware peripherals -- References -- Chapter 8: Exceptions and interrupts-Architecture overview -- 8.1. Overview of exceptions and interrupts -- 8.1.1. The need for exceptions and interrupts 8.1.2. Basic concepts of peripheral interrupt operations Embedded computer systems ARM Cortex-M (DE-588)1129794121 gnd rswk-swf Mikroprozessor (DE-588)4039232-6 gnd rswk-swf Eingebettetes System (DE-588)4396978-1 gnd rswk-swf ARM Computerarchitektur (DE-588)4706184-4 gnd rswk-swf Mikrocontroller (DE-588)4127438-6 gnd rswk-swf ARM Computerarchitektur (DE-588)4706184-4 s Mikrocontroller (DE-588)4127438-6 s Eingebettetes System (DE-588)4396978-1 s DE-604 Mikroprozessor (DE-588)4039232-6 s ARM Cortex-M (DE-588)1129794121 s Erscheint auch als Yiu, Joseph Definitive Guide to Arm Cortex-M23 and Cortex-M33 Processors San Diego : Elsevier Science & Technology,c2020 Druck-Ausgabe 978-0-12-820735-2 |
| spellingShingle | Yiu, Joseph Definitive guide to ARM Cortex-M23 and Cortex-M33 processors Intro -- Definitive Guide to Arm Cortex-M23 and Cortex-M33 Processors -- Copyright -- Dedication -- Contents -- Preface -- Contributing author: Paul Beckmann -- Acknowledgments -- Chapter 1: Introduction -- 1.1. Microcontrollers and processors -- 1.2. Classification of processors -- 1.3. The Cortex-M23 and Cortex-M33 processors and the Armv8-M architecture -- 1.4. Characteristics of the Cortex-M23 and Cortex-M33 processors -- 1.5. Why have two different processors? -- 1.6. Applications of the Cortex-M23 and Cortex-M33 -- 1.7. Technical features -- 1.8. Comparison with previous generations of Cortex-M processors -- 1.9. Advantages of the Cortex-M23 and Cortex-M33 processors -- 1.10. Understanding microcontroller programming -- 1.11. Further reading -- 1.11.1. Product pages on developer.arm.com -- 1.11.2. Documentation on developer.arm.com -- 1.11.3. Community.arm.com -- References -- Chapter 2: Getting started with Cortex-M programming -- 2.1. Overview -- 2.1.1. Development suites -- 2.1.2. Development board -- 2.1.3. Debug adaptor -- 2.1.4. Resources -- 2.2. Some basic concepts -- 2.2.1. Reset -- 2.2.2. Clocks -- 2.2.3. Voltage level -- 2.2.4. Inputs and outputs -- 2.2.5. Introduction to embedded software program flows -- 2.2.5.1. Polling method -- 2.2.5.2. Interrupt driven method -- 2.2.5.3. Combination of polling and interrupt-driven methods -- 2.2.5.4. Handling concurrent processes -- 2.3. Introduction to Arm Cortex-M programming -- 2.3.1. C Programming-Data types -- 2.3.2. Accessing peripherals in C -- 2.3.3. What is inside a program image? -- 2.3.3.1. Vector table -- 2.3.3.2. Reset handler/startup code -- 2.3.3.3. C startup code -- 2.3.3.4. Application code -- 2.3.3.5. C library code -- 2.3.3.6. Other data -- 2.3.4. Data in SRAM -- 2.3.5. What happens when a microcontroller starts? -- 2.3.6. Understanding your hardware platform 2.4. Software development flow -- 2.5. Cortex Microcontroller Software Interface Standard (CMSIS) -- 2.5.1. Introduction of CMSIS -- 2.5.2. What is standardized in the CMSIS-CORE? -- 2.5.3. Using CMSIS-CORE -- 2.5.4. Benefits of CMSIS -- 2.6. Additional information on software development -- Reference -- Chapter 3: Technical overview of the Cortex-M23 and Cortex-M33 processors -- 3.1. Design objectives of Cortex-M23 and Cortex-M33 processors -- 3.2. Block diagrams -- 3.2.1. Cortex-M23 -- 3.2.2. Cortex-M33 -- 3.3. Processor -- 3.4. Instruction set -- 3.5. Memory map -- 3.6. Bus interfaces -- 3.7. Memory protection -- 3.8. Interrupt and exception handling -- 3.9. Low power features -- 3.10. OS support features -- 3.11. Floating-point unit -- 3.12. Coprocessor interface and Arm Custom Instructions -- 3.13. Debug and trace support -- 3.14. Multicore system design support -- 3.15. Key feature enhancements in Cortex-M23 and Cortex-M33 processors -- 3.15.1. Comparison between Cortex-M0+ and Cortex-M23 processors -- 3.15.2. Comparison between Cortex-M3/M4 and Cortex-M33 processors -- 3.16. Compatibility with other Cortex-M processors -- 3.17. Processor configuration options -- 3.18. Introduction to TrustZone -- 3.18.1. Overview of security requirements -- 3.18.2. Evolution of security in embedded systems -- 3.18.3. TrustZone for Armv8-M -- 3.19. Why TrustZone enables better security? -- 3.20. Firmware asset protection with eXecute-Only-Memory (XOM) -- Reference -- Chapter 4: Architecture -- 4.1. Introduction to the Armv8-M architecture -- 4.1.1. Overview -- 4.1.2. Background to the Armv8-M architecture -- 4.2. Programmer's model -- 4.2.1. Processor modes and states -- 4.2.2. Registers -- 4.2.2.1. Various types of registers -- 4.2.2.2. Registers in the register bank -- 4.2.2.3. Special registers -- Program Status Register (PSR) -- Interrupt masking registers CONTROL register -- Stack limit registers -- 4.2.2.4. Floating-point registers in Cortex-M33 -- 4.2.3. Behaviors of the APSR (ALU status flags) -- 4.2.3.1. Integer status flags -- 4.2.3.2. Q status flag -- 4.2.3.3. GE bits -- 4.2.4. Impact of TrustZone on the programmer's model -- 4.3. Memory system -- 4.3.1. Memory map -- 4.3.2. Partitioning of address spaces within TrustZone -- 4.3.3. System control space (SCS) and system control block (SCB) -- 4.3.4. Stack memory -- 4.3.5. Setting up and accessing of stack pointers and stack limit registers -- 4.3.6. Memory protection unit (MPU) -- 4.4. Exceptions and Interrupts -- 4.4.1. What are exceptions -- 4.4.2. TrustZone and exceptions -- 4.4.3. Nested Vectored Interrupt Controller (NVIC) -- 4.4.3.1. Flexible exception and interrupt management -- 4.4.3.2. Nested exception/interrupt support -- 4.4.3.3. Vectored exception/interrupt entry -- 4.4.3.4. Interrupt masking -- 4.4.4. Interrupt management with CMSIS-CORE -- 4.4.5. Vector tables -- 4.4.6. Fault handling -- 4.5. Debug -- 4.6. Reset and reset sequence -- 4.7. Other related architecture information -- References -- Chapter 5: Instruction set -- 5.1. Background -- 5.1.1. About this chapter -- 5.1.2. Background to the Instruction set in Arm Cortex-M processors -- 5.2. Instruction set features in various Cortex-M processors -- 5.3. Understanding the assembly language syntax -- 5.4. Use of a suffix in an instruction -- 5.5. Unified Assembly Language (UAL) -- 5.6. Instruction set-Moving data within the processors -- 5.6.1. Overview -- 5.6.2. Moving data between registers -- 5.6.3. Immediate data generation -- 5.6.4. Special register access instructions -- 5.6.5. Floating point register access -- 5.6.6. Floating point immediate data generation -- 5.6.7. Moving data between a register and a coprocessor register -- 5.7. Instruction set-Memory access 5.7.1. Overview -- 5.7.2. Single memory access -- 5.7.3. SP relative load/stores -- 5.7.4. Preindexed and postindex addressing modes -- 5.7.5. Optional shift in register offset (Barrel shifter) -- 5.7.6. Literal data read -- 5.7.7. Multiple load/store -- 5.7.8. PUSH/POP -- 5.7.9. Unprivileged access instructions -- 5.7.10. FPU memory access instructions -- 5.7.11. Exclusive access -- 5.7.12. Load acquire-store release -- 5.8. Instruction set-Arithmetic operations -- 5.9. Instruction set-Logic operations -- 5.10. Instruction set-Shift and rotate operations -- 5.11. Instruction set-Data conversions (extend and reverse ordering) -- 5.12. Instruction set-Bit field processing -- 5.13. Instruction set-Saturation operations -- 5.14. Instruction set-Program flow control -- 5.14.1. Overview -- 5.14.2. Branch -- 5.14.3. Function call -- 5.14.4. Conditional branch -- 5.14.5. Compare and branches (CBZ, CBNZ) -- 5.14.6. Conditional execution (IF-THEN instruction block) -- 5.14.7. Table branches (TBB and TBH) -- 5.15. Instruction set-DSP extension -- 5.15.1. Overview -- 5.15.2. SIMD concept -- 5.15.3. SIMD and saturating arithmetic instructions -- 5.15.4. Multiply and MAC instructions -- 5.15.5. Packing and unpacking instructions -- 5.16. Instruction set-Floating point support instructions -- 5.16.1. Overview of floating-point support in Armv8-M processors -- 5.16.2. Enabling the FPU -- 5.16.3. Floating point instructions -- 5.17. Instruction set-Exception-related instructions -- 5.18. Instruction set-Sleep mode-related instructions -- 5.19. Instruction set-Memory barrier instructions -- 5.20. Instruction set-TrustZone support instructions -- 5.21. Instruction set-Coprocessor and Arm custom instructions support -- 5.22. Instruction set-Other functions -- 5.23. Accessing special registers with the CMSIS-CORE -- References -- Chapter 6: Memory system 6.1. Overview of the memory system -- 6.1.1. What is in the memory system? -- 6.1.2. Memory system features -- 6.1.3. Key changes for the Cortex-M23/M33 when compared to the previous Cortex-M processors -- 6.2. Memory map -- 6.3. Memory types and memory attributes -- 6.3.1. Memory type classifications -- 6.3.2. Memory attributes overview -- 6.3.3. Memory attributes of the default memory map -- 6.4. Access permission management -- 6.4.1. Overview of access permission management -- 6.4.2. Access control mechanisms -- 6.4.3. Differences between the SAU/IDAU and the MPU -- 6.4.4. Default access permission -- 6.5. Memory endianness -- 6.6. Data alignment and unaligned data access support -- 6.7. Exclusive access support -- 6.8. Memory ordering and memory barrier instructions -- 6.9. Bus wait state and error support -- 6.10. Single-cycle I/O port-Cortex-M23 only -- 6.11. Memory systems in microcontrollers -- 6.11.1. Memory requirements -- 6.11.2. Bus system designs -- 6.11.3. Security management -- 6.12. Software considerations -- 6.12.1. Bus level power management -- 6.12.2. TrustZone security -- 6.12.3. Use of multiple load and store instructions -- References -- Chapter 7: TrustZone support in the memory system -- 7.1. Overview -- 7.1.1. About this chapter -- 7.1.2. Memory security attributes -- 7.2. SAU and IDAU -- 7.3. Banked and nonbanked registers -- 7.3.1. Overview -- 7.3.2. System Control Space (SCS) NS alias -- 7.4. Test Target (TT) instructions and region ID numbers -- 7.4.1. Why are the TT instructions needed? -- 7.4.2. The TT instructions -- 7.4.3. Region ID numbers -- 7.5. Memory protection controller and peripheral protection controller -- 7.6. Security aware peripherals -- References -- Chapter 8: Exceptions and interrupts-Architecture overview -- 8.1. Overview of exceptions and interrupts -- 8.1.1. The need for exceptions and interrupts 8.1.2. Basic concepts of peripheral interrupt operations Embedded computer systems ARM Cortex-M (DE-588)1129794121 gnd Mikroprozessor (DE-588)4039232-6 gnd Eingebettetes System (DE-588)4396978-1 gnd ARM Computerarchitektur (DE-588)4706184-4 gnd Mikrocontroller (DE-588)4127438-6 gnd |
| subject_GND | (DE-588)1129794121 (DE-588)4039232-6 (DE-588)4396978-1 (DE-588)4706184-4 (DE-588)4127438-6 |
| title | Definitive guide to ARM Cortex-M23 and Cortex-M33 processors |
| title_auth | Definitive guide to ARM Cortex-M23 and Cortex-M33 processors |
| title_exact_search | Definitive guide to ARM Cortex-M23 and Cortex-M33 processors |
| title_exact_search_txtP | Definitive guide to ARM Cortex-M23 and Cortex-M33 processors |
| title_full | Definitive guide to ARM Cortex-M23 and Cortex-M33 processors Joseph Yiu |
| title_fullStr | Definitive guide to ARM Cortex-M23 and Cortex-M33 processors Joseph Yiu |
| title_full_unstemmed | Definitive guide to ARM Cortex-M23 and Cortex-M33 processors Joseph Yiu |
| title_short | Definitive guide to ARM Cortex-M23 and Cortex-M33 processors |
| title_sort | definitive guide to arm cortex m23 and cortex m33 processors |
| topic | Embedded computer systems ARM Cortex-M (DE-588)1129794121 gnd Mikroprozessor (DE-588)4039232-6 gnd Eingebettetes System (DE-588)4396978-1 gnd ARM Computerarchitektur (DE-588)4706184-4 gnd Mikrocontroller (DE-588)4127438-6 gnd |
| topic_facet | Embedded computer systems ARM Cortex-M Mikroprozessor Eingebettetes System ARM Computerarchitektur Mikrocontroller |
| work_keys_str_mv | AT yiujoseph definitiveguidetoarmcortexm23andcortexm33processors |