Reversible and DNA computing:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Hoboken, NJ, USA ; Chichester, West Sussex, UK
Wiley
2021
|
| Schlagworte: | |
| Online-Zugang: | TUM01 |
| Beschreibung: | Description based on publisher supplied metadata and other sources |
| Beschreibung: | 1 Online-Ressource (xl, 392 Seiten) Illustrationen, Diagramme |
| ISBN: | 9781119679363 9781119679431 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV047441882 | ||
| 003 | DE-604 | ||
| 005 | 20240220 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 210827s2021 |||| o||u| ||||||eng d | ||
| 020 | |a 9781119679363 |9 978-1-119-67936-3 | ||
| 020 | |a 9781119679431 |9 978-1-119-67943-1 | ||
| 035 | |a (ZDB-30-PQE)EBC6301548 | ||
| 035 | |a (ZDB-30-PAD)EBC6301548 | ||
| 035 | |a (ZDB-89-EBL)EBL6301548 | ||
| 035 | |a (OCoLC)1203962948 | ||
| 035 | |a (DE-599)BVBBV047441882 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91 | ||
| 082 | 0 | |a 006.3842 | |
| 084 | |a PHY 821 |2 stub | ||
| 084 | |a DAT 200 |2 stub | ||
| 100 | 1 | |a Babu, Hafiz Md. Hasan |d 1966- |e Verfasser |0 (DE-588)1217495320 |4 aut | |
| 245 | 1 | 0 | |a Reversible and DNA computing |c Hafiz Md. Hasan Babu |
| 264 | 1 | |a Hoboken, NJ, USA ; Chichester, West Sussex, UK |b Wiley |c 2021 | |
| 264 | 4 | |c © 2021 | |
| 300 | |a 1 Online-Ressource (xl, 392 Seiten) |b Illustrationen, Diagramme | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Description based on publisher supplied metadata and other sources | ||
| 505 | 8 | |a Cover -- Title Page -- Copyright -- Contents -- List of Figures -- List of Tables -- About the Author -- Preface -- Acknowledgments -- Acronyms -- Introduction -- Part I Reversible Circuits -- An Overview About Reversible Circuits -- Chapter 1 Reversible Logic Synthesis -- 1.1 Reversible Logic -- 1.2 Reversible Function -- 1.3 Reversible Logic Gate -- 1.4 Garbage Outputs -- 1.5 Constant Inputs -- 1.6 Quantum Cost -- 1.7 Delay -- 1.8 Power -- 1.9 Area -- 1.10 Hardware Complexity -- 1.11 Quantum Gate Calculation Complexity -- 1.12 Fan-Out -- 1.13 Self-Reversible -- 1.14 Reversible Computation -- 1.15 Area -- 1.16 Design Constraints for Reversible Logic Circuits -- 1.17 Quantum Analysis of Different Reversible Logic Gates -- 1.17.1 Reversible NOT Gate (Feynman Gate) -- 1.17.2 Toffoli Gate -- 1.17.3 Fredkin Gate -- 1.17.4 Peres Gate -- 1.18 Summary -- Chapter 2 Reversible Adder and Subtractor Circuits -- 2.1 Reversible Multi-Operand n-Digit Decimal Adder -- 2.1.1 Full Adder -- 2.1.1.0 The FAG Gate -- 2.1.1.0 Reversible FAG Gate as Full Adder -- 2.1.2 Carry Skip Adder -- 2.1.2.1 Design of Carry Skip Adder -- 2.1.3 Carry Look-Ahead Adder -- 2.2 Reversible BCD Adders -- 2.2.1 Design Procedure of the Reversible BCD Adder -- 2.2.1.1 Properties of the Reversible BCD Adder -- 2.2.2 Design Procedure of the Reversible Carry Skip BCD Adder -- 2.2.2.1 Properties of the Reversible Carry Skip BCD Adder -- 2.3 Reversible BCD Subtractor -- 2.3.1 Carry Look-Ahead BCD Subtractor -- 2.3.2 Carry Skip BCD Subtractor -- 2.3.3 Design of Conventional Reversible BCD Subtractor -- 2.3.3.1 Reversible Nine's Complement -- 2.3.3.2 Reversible BCD Subtractor -- 2.3.3.3 Reversible Design of Carry Look-Ahead BCD Subtractor -- 2.3.3.4 Reversible Design of Carry Skip BCD Subtractor -- 2.4 Summary -- Chapter 3 Reversible Multiplier Circuit -- 3.1 Multiplication Using Booth's Recoding | |
| 505 | 8 | |a 3.2 Reversible Gates as Half Adders and Full Adders -- 3.3 Some Signed Reversible Multipliers -- 3.4 Design of Reversible Multiplier Circuit -- 3.4.1 Some Quantum Gates -- 3.4.2 Recoding Cell -- 3.4.3 Partial Product Generation Circuit -- 3.4.4 Multi-Operand Addition Circuit -- 3.4.5 Calculation of Area and Power of n×n Multiplier Circuit -- 3.5 Summary -- Chapter 4 Reversible Division Circuit -- 4.1 The Division Approaches -- 4.1.1 Restoring Division -- 4.1.2 Nonrestoring Division -- 4.2 Components of Division Circuit -- 4.2.1 Reversible MUX -- 4.2.2 Reversible Register -- 4.2.3 Reversible PIPO Left-Shift Register -- 4.2.4 Reversible Parallel Adder -- 4.3 The Design of Reversible Division Circuit -- 4.4 Summary -- Chapter 5 Reversible Binary Comparator -- 5.1 Design of Reversible n-Bit Comparator -- 5.1.1 BJS Gate -- 5.1.2 Reversible 1-Bit Comparator Circuit -- 5.1.3 Reversible MSB Comparator Circuit -- 5.1.4 Reversible Single-Bit Greater or Equal Comparator Cell -- 5.1.5 Reversible Single-Bit Less Than Comparator Cell -- 5.1.6 Reversible 2-Bit Comparator Circuit -- 5.1.7 Reversible n-Bit Comparator Circuit -- 5.2 Summary -- Chapter 6 Reversible Sequential Circuits -- 6.1 An Example of Design Methodology -- 6.2 The Design of Reversible Latches -- 6.2.1 The SR Latch -- 6.2.2 The D Latch -- 6.2.2.1 The D Latch with Outputs Q and Q‾ -- 6.2.2.2 The Negative Enable Reversible D Latch -- 6.2.3 T Latch -- 6.2.4 The JK Latch -- 6.3 The Design of Reversible Master-Slave Flip-Flops -- 6.4 The Design of Reversible Latch and the Master-Slave Flip-Flop with Asynchronous SET and RESET Capabilities -- 6.5 Summary -- Chapter 7 Reversible Counter, Decoder, and Encoder Circuits -- 7.1 Synthesis of Reversible Counter -- 7.1.1 Reversible T Flip-Flop -- 7.1.2 Reversible Clocked T Flip-Flop -- 7.1.3 Reversible Master-Slave T Flip-Flop | |
| 505 | 8 | |a 7.1.4 Reversible Asynchronous Counter -- 7.1.5 Reversible Synchronous Counter -- 7.2 Reversible Decoder -- 7.2.1 Reversible Encoder -- 7.3 Summary -- Chapter 8 Reversible Barrel Shifter and Shift Register -- 8.1 Design Procedure of Reversible Bidirectional Barrel Shifter -- 8.1.1 Reversible 3 × 3 Modified BJN Gate -- 8.1.2 Reversible 2's Complement Generator -- 8.1.3 Reversible Swap Condition Generator -- 8.1.4 Reversible Right Rotator -- 8.1.4.1 (4, 3) Reversible Right Rotator -- 8.1.4.2 Generalized Reversible Right Rotator -- 8.1.5 Reversible Bidirectional Barrel Shifter -- 8.2 Design Procedure of Reversible Shift Register -- 8.2.1 Reversible Flip-Flop -- 8.2.1.1 Reversible SISO Shift Register -- 8.2.1.2 Reversible SIPO Shift Register -- 8.2.1.3 Reversible PISO Shift Register -- 8.2.1.4 Reversible PIPO Shift Register -- 8.2.1.5 Reversible Universal Shift Register -- 8.3 Summary -- Chapter 9 Reversible Multiplexer and Demultiplexer with Other Logical Operations -- 9.1 Reversible Logic Gates -- 9.1.1 RG1 Gate -- 9.1.2 RG2 Gate -- 9.2 Designs of Reversible Multiplexer and Demultiplexer with Other Logical Operations -- 9.2.1 The R-I Gate -- 9.2.2 The R-II Gate -- 9.3 Summary -- Chapter 10 Reversible Programmable Logic Devices -- 10.1 Reversible FPGA -- 10.1.1 3×3 Reversible NH Gate -- 10.1.2 4 × 4 Reversible BSP Gate -- 10.1.3 4-to-1 Reversible Multiplexer -- 10.1.4 Reversible D Latch -- 10.1.5 Reversible Write-Enabled Master-Slave Flip-Flop -- 10.1.6 Reversible RAM -- 10.1.7 Design of Reversible FPGA -- 10.2 Reversible PLA -- 10.2.1 The Design Procedure -- 10.2.1.1 Delay Calculation of a Reversible PLA -- 10.2.1.2 Delay Calculation of AND Plane -- 10.2.1.3 Delay Calculation of Ex-OR Plane -- 10.2.1.4 Delay of Overall Design -- 10.3 Summary -- Chapter 11 Reversible RAM and Programmable ROM -- 11.1 Reversible RAM -- 11.1.1 3×3 Reversible FS Gate | |
| 505 | 8 | |a 11.1.2 Reversible Decoder -- 11.1.3 Reversible D Flip-Flop -- 11.1.4 Reversible Write-Enabled Master-Slave D Flip-Flop -- 11.1.5 Reversible Random Access Memory -- 11.2 Reversible PROM -- 11.2.1 Reversible Decoder -- 11.2.2 Design of Reversible PROM -- 11.3 Summary -- Chapter 12 Reversible Arithmetic Logic Unit -- 12.1 Design of ALU -- 12.1.1 Conventional ALU -- 12.1.2 The ALU Based on Reversible Logic -- 12.1.2.1 The Reversible Function Generator -- 12.1.2.2 The Reversible Control Unit -- 12.2 Design of Reversible ALU -- 12.3 Summary -- Chapter 13 Reversible Control Unit -- 13.1 An Example of Control Unit -- 13.2 Different Components of a Control Unit -- 13.2.1 Reversible HL Gate -- 13.2.2 Reversible BJ Gate -- 13.2.3 Reversible 2-to-4 Decoder -- 13.2.4 Reversible 3-to-8 Decoder -- 13.2.5 Reversible n-to-2n Decoder -- 13.2.6 Reversible JK Flip-Flop -- 13.2.7 Reversible Sequence Counter -- 13.2.8 Reversible Instruction Register -- 13.2.9 Control of Registers and Memory -- 13.2.10 Construction Procedure and Complexities of the Control Unit -- 13.3 Summary -- Part II Reversible Fault Tolerance -- An Overview About Fault-Tolerance and Testable Circuits -- Chapter 14 Reversible Fault-Tolerant Adder Circuits -- 14.1 Properties of Fault Tolerance -- 14.1.1 Parity-Preserving Reversible Gates -- 14.2 Reversible Parity-Preserving Adders -- 14.2.1 Fault-Tolerant Full Adder -- 14.2.2 Fault-Tolerant Carry Skip Adder -- 14.2.3 Fault-Tolerant Carry Look-Ahead Adder -- 14.2.4 Fault-Tolerant Ripple Carry Adder -- 14.3 Summary -- Chapter 15 Reversible Fault-Tolerant Multiplier Circuit -- 15.1 Reversible Fault-Tolerant Multipliers -- 15.1.1 Reversible Fault-Tolerant n×n Multiplier -- 15.1.2 LMH Gate -- 15.1.3 Partial Product Generation -- 15.1.4 Multi-Operand Addition -- 15.2 Summary -- Chapter 16 Reversible Fault-Tolerant Division Circuit | |
| 505 | 8 | |a 16.1 Preliminaries of Division Circuits -- 16.1.1 Division Algorithms -- 16.2 The Division Method -- 16.2.1 Floating-Point Data and Rounding -- 16.2.2 Correctly Rounded Division -- 16.2.3 Correct Rounding from One-Sided Approximations -- 16.2.4 The Algorithm for Division Operation -- 16.3 Components of a Division Circuit -- 16.3.1 Reversible Fault-Tolerant MUX -- 16.3.2 Reversible Fault-Tolerant D Latch -- 16.4 The Design of the Division Circuit -- 16.4.1 Reversible Fault-Tolerant PIPO Left‐Shift Register -- 16.4.2 Reversible Fault-Tolerant Register -- 16.4.3 Reversible Fault-Tolerant Rounding Register -- 16.4.4 Reversible Fault-Tolerant Normalization Register -- 16.4.5 Reversible Fault-Tolerant Parallel Adder -- 16.4.6 The Reversible Fault-Tolerant Division Circuit -- 16.5 Summary -- Chapter 17 Reversible Fault-Tolerant Decoder Circuit -- 17.1 Transistor Realization of Some Popular Reversible Gates -- 17.1.1 Feynman Double Gate -- 17.1.2 Fredkin Gate -- 17.2 Reversible Fault-Tolerant Decoder -- 17.3 Summary -- Chapter 18 Reversible Fault-Tolerant Barrel Shifter -- 18.1 Properties of Barrel Shifters -- 18.2 Reversible Fault-Tolerant Unidirectional Logarithmic Rotators -- 18.3 Fault-Tolerant Unidirectional Logarithmic Logical Shifters -- 18.4 Summary -- Chapter 19 Reversible Fault-Tolerant Programmable Logic Devices -- 19.1 Reversible Fault-Tolerant Programmable Logic Array -- 19.1.1 The Design of RFTPLA -- 19.2 Reversible Fault-Tolerant Programmable Array Logic -- 19.2.1 The Design of AND Plane of RFTPAL -- 19.2.2 The Design of Ex-OR Plane of RFTPAL -- 19.3 Reversible Fault-Tolerant LUT-Based FPGA -- 19.3.1 Reversible Fault-Tolerant Gates -- 19.3.2 Proof of Fault-Tolerance Properties of the MSH and MSB Gates -- 19.3.3 Physical Implementation of the Gates -- 19.3.4 Reversible Fault-Tolerant D Latch, Master-Slave Flip-Flop and 4×1 Multiplexer | |
| 505 | 8 | |a 19.3.5 Reversible Fault-Tolerant n-Input Look-Up Table | |
| 650 | 4 | |a Molecular computers | |
| 776 | 0 | 8 | |i Erscheint auch als |a Babu, Hafiz M, H |t Reversible and DNA Computing |d Newark : John Wiley & Sons, Incorporated,c2020 |n Druck-Ausgabe, Hardcover |z 978-1-119-67942-4 |
| 912 | |a ZDB-30-PQE | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-032844034 | ||
| 966 | e | |u https://ebookcentral.proquest.com/lib/munchentech/detail.action?docID=6301548 |l TUM01 |p ZDB-30-PQE |q TUM_PDA_PQE_Kauf |x Aggregator |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804182734614036480 |
|---|---|
| adam_txt | |
| any_adam_object | |
| any_adam_object_boolean | |
| author | Babu, Hafiz Md. Hasan 1966- |
| author_GND | (DE-588)1217495320 |
| author_facet | Babu, Hafiz Md. Hasan 1966- |
| author_role | aut |
| author_sort | Babu, Hafiz Md. Hasan 1966- |
| author_variant | h m h b hmh hmhb |
| building | Verbundindex |
| bvnumber | BV047441882 |
| classification_tum | PHY 821 DAT 200 |
| collection | ZDB-30-PQE |
| contents | Cover -- Title Page -- Copyright -- Contents -- List of Figures -- List of Tables -- About the Author -- Preface -- Acknowledgments -- Acronyms -- Introduction -- Part I Reversible Circuits -- An Overview About Reversible Circuits -- Chapter 1 Reversible Logic Synthesis -- 1.1 Reversible Logic -- 1.2 Reversible Function -- 1.3 Reversible Logic Gate -- 1.4 Garbage Outputs -- 1.5 Constant Inputs -- 1.6 Quantum Cost -- 1.7 Delay -- 1.8 Power -- 1.9 Area -- 1.10 Hardware Complexity -- 1.11 Quantum Gate Calculation Complexity -- 1.12 Fan-Out -- 1.13 Self-Reversible -- 1.14 Reversible Computation -- 1.15 Area -- 1.16 Design Constraints for Reversible Logic Circuits -- 1.17 Quantum Analysis of Different Reversible Logic Gates -- 1.17.1 Reversible NOT Gate (Feynman Gate) -- 1.17.2 Toffoli Gate -- 1.17.3 Fredkin Gate -- 1.17.4 Peres Gate -- 1.18 Summary -- Chapter 2 Reversible Adder and Subtractor Circuits -- 2.1 Reversible Multi-Operand n-Digit Decimal Adder -- 2.1.1 Full Adder -- 2.1.1.0 The FAG Gate -- 2.1.1.0 Reversible FAG Gate as Full Adder -- 2.1.2 Carry Skip Adder -- 2.1.2.1 Design of Carry Skip Adder -- 2.1.3 Carry Look-Ahead Adder -- 2.2 Reversible BCD Adders -- 2.2.1 Design Procedure of the Reversible BCD Adder -- 2.2.1.1 Properties of the Reversible BCD Adder -- 2.2.2 Design Procedure of the Reversible Carry Skip BCD Adder -- 2.2.2.1 Properties of the Reversible Carry Skip BCD Adder -- 2.3 Reversible BCD Subtractor -- 2.3.1 Carry Look-Ahead BCD Subtractor -- 2.3.2 Carry Skip BCD Subtractor -- 2.3.3 Design of Conventional Reversible BCD Subtractor -- 2.3.3.1 Reversible Nine's Complement -- 2.3.3.2 Reversible BCD Subtractor -- 2.3.3.3 Reversible Design of Carry Look-Ahead BCD Subtractor -- 2.3.3.4 Reversible Design of Carry Skip BCD Subtractor -- 2.4 Summary -- Chapter 3 Reversible Multiplier Circuit -- 3.1 Multiplication Using Booth's Recoding 3.2 Reversible Gates as Half Adders and Full Adders -- 3.3 Some Signed Reversible Multipliers -- 3.4 Design of Reversible Multiplier Circuit -- 3.4.1 Some Quantum Gates -- 3.4.2 Recoding Cell -- 3.4.3 Partial Product Generation Circuit -- 3.4.4 Multi-Operand Addition Circuit -- 3.4.5 Calculation of Area and Power of n×n Multiplier Circuit -- 3.5 Summary -- Chapter 4 Reversible Division Circuit -- 4.1 The Division Approaches -- 4.1.1 Restoring Division -- 4.1.2 Nonrestoring Division -- 4.2 Components of Division Circuit -- 4.2.1 Reversible MUX -- 4.2.2 Reversible Register -- 4.2.3 Reversible PIPO Left-Shift Register -- 4.2.4 Reversible Parallel Adder -- 4.3 The Design of Reversible Division Circuit -- 4.4 Summary -- Chapter 5 Reversible Binary Comparator -- 5.1 Design of Reversible n-Bit Comparator -- 5.1.1 BJS Gate -- 5.1.2 Reversible 1-Bit Comparator Circuit -- 5.1.3 Reversible MSB Comparator Circuit -- 5.1.4 Reversible Single-Bit Greater or Equal Comparator Cell -- 5.1.5 Reversible Single-Bit Less Than Comparator Cell -- 5.1.6 Reversible 2-Bit Comparator Circuit -- 5.1.7 Reversible n-Bit Comparator Circuit -- 5.2 Summary -- Chapter 6 Reversible Sequential Circuits -- 6.1 An Example of Design Methodology -- 6.2 The Design of Reversible Latches -- 6.2.1 The SR Latch -- 6.2.2 The D Latch -- 6.2.2.1 The D Latch with Outputs Q and Q‾ -- 6.2.2.2 The Negative Enable Reversible D Latch -- 6.2.3 T Latch -- 6.2.4 The JK Latch -- 6.3 The Design of Reversible Master-Slave Flip-Flops -- 6.4 The Design of Reversible Latch and the Master-Slave Flip-Flop with Asynchronous SET and RESET Capabilities -- 6.5 Summary -- Chapter 7 Reversible Counter, Decoder, and Encoder Circuits -- 7.1 Synthesis of Reversible Counter -- 7.1.1 Reversible T Flip-Flop -- 7.1.2 Reversible Clocked T Flip-Flop -- 7.1.3 Reversible Master-Slave T Flip-Flop 7.1.4 Reversible Asynchronous Counter -- 7.1.5 Reversible Synchronous Counter -- 7.2 Reversible Decoder -- 7.2.1 Reversible Encoder -- 7.3 Summary -- Chapter 8 Reversible Barrel Shifter and Shift Register -- 8.1 Design Procedure of Reversible Bidirectional Barrel Shifter -- 8.1.1 Reversible 3 × 3 Modified BJN Gate -- 8.1.2 Reversible 2's Complement Generator -- 8.1.3 Reversible Swap Condition Generator -- 8.1.4 Reversible Right Rotator -- 8.1.4.1 (4, 3) Reversible Right Rotator -- 8.1.4.2 Generalized Reversible Right Rotator -- 8.1.5 Reversible Bidirectional Barrel Shifter -- 8.2 Design Procedure of Reversible Shift Register -- 8.2.1 Reversible Flip-Flop -- 8.2.1.1 Reversible SISO Shift Register -- 8.2.1.2 Reversible SIPO Shift Register -- 8.2.1.3 Reversible PISO Shift Register -- 8.2.1.4 Reversible PIPO Shift Register -- 8.2.1.5 Reversible Universal Shift Register -- 8.3 Summary -- Chapter 9 Reversible Multiplexer and Demultiplexer with Other Logical Operations -- 9.1 Reversible Logic Gates -- 9.1.1 RG1 Gate -- 9.1.2 RG2 Gate -- 9.2 Designs of Reversible Multiplexer and Demultiplexer with Other Logical Operations -- 9.2.1 The R-I Gate -- 9.2.2 The R-II Gate -- 9.3 Summary -- Chapter 10 Reversible Programmable Logic Devices -- 10.1 Reversible FPGA -- 10.1.1 3×3 Reversible NH Gate -- 10.1.2 4 × 4 Reversible BSP Gate -- 10.1.3 4-to-1 Reversible Multiplexer -- 10.1.4 Reversible D Latch -- 10.1.5 Reversible Write-Enabled Master-Slave Flip-Flop -- 10.1.6 Reversible RAM -- 10.1.7 Design of Reversible FPGA -- 10.2 Reversible PLA -- 10.2.1 The Design Procedure -- 10.2.1.1 Delay Calculation of a Reversible PLA -- 10.2.1.2 Delay Calculation of AND Plane -- 10.2.1.3 Delay Calculation of Ex-OR Plane -- 10.2.1.4 Delay of Overall Design -- 10.3 Summary -- Chapter 11 Reversible RAM and Programmable ROM -- 11.1 Reversible RAM -- 11.1.1 3×3 Reversible FS Gate 11.1.2 Reversible Decoder -- 11.1.3 Reversible D Flip-Flop -- 11.1.4 Reversible Write-Enabled Master-Slave D Flip-Flop -- 11.1.5 Reversible Random Access Memory -- 11.2 Reversible PROM -- 11.2.1 Reversible Decoder -- 11.2.2 Design of Reversible PROM -- 11.3 Summary -- Chapter 12 Reversible Arithmetic Logic Unit -- 12.1 Design of ALU -- 12.1.1 Conventional ALU -- 12.1.2 The ALU Based on Reversible Logic -- 12.1.2.1 The Reversible Function Generator -- 12.1.2.2 The Reversible Control Unit -- 12.2 Design of Reversible ALU -- 12.3 Summary -- Chapter 13 Reversible Control Unit -- 13.1 An Example of Control Unit -- 13.2 Different Components of a Control Unit -- 13.2.1 Reversible HL Gate -- 13.2.2 Reversible BJ Gate -- 13.2.3 Reversible 2-to-4 Decoder -- 13.2.4 Reversible 3-to-8 Decoder -- 13.2.5 Reversible n-to-2n Decoder -- 13.2.6 Reversible JK Flip-Flop -- 13.2.7 Reversible Sequence Counter -- 13.2.8 Reversible Instruction Register -- 13.2.9 Control of Registers and Memory -- 13.2.10 Construction Procedure and Complexities of the Control Unit -- 13.3 Summary -- Part II Reversible Fault Tolerance -- An Overview About Fault-Tolerance and Testable Circuits -- Chapter 14 Reversible Fault-Tolerant Adder Circuits -- 14.1 Properties of Fault Tolerance -- 14.1.1 Parity-Preserving Reversible Gates -- 14.2 Reversible Parity-Preserving Adders -- 14.2.1 Fault-Tolerant Full Adder -- 14.2.2 Fault-Tolerant Carry Skip Adder -- 14.2.3 Fault-Tolerant Carry Look-Ahead Adder -- 14.2.4 Fault-Tolerant Ripple Carry Adder -- 14.3 Summary -- Chapter 15 Reversible Fault-Tolerant Multiplier Circuit -- 15.1 Reversible Fault-Tolerant Multipliers -- 15.1.1 Reversible Fault-Tolerant n×n Multiplier -- 15.1.2 LMH Gate -- 15.1.3 Partial Product Generation -- 15.1.4 Multi-Operand Addition -- 15.2 Summary -- Chapter 16 Reversible Fault-Tolerant Division Circuit 16.1 Preliminaries of Division Circuits -- 16.1.1 Division Algorithms -- 16.2 The Division Method -- 16.2.1 Floating-Point Data and Rounding -- 16.2.2 Correctly Rounded Division -- 16.2.3 Correct Rounding from One-Sided Approximations -- 16.2.4 The Algorithm for Division Operation -- 16.3 Components of a Division Circuit -- 16.3.1 Reversible Fault-Tolerant MUX -- 16.3.2 Reversible Fault-Tolerant D Latch -- 16.4 The Design of the Division Circuit -- 16.4.1 Reversible Fault-Tolerant PIPO Left‐Shift Register -- 16.4.2 Reversible Fault-Tolerant Register -- 16.4.3 Reversible Fault-Tolerant Rounding Register -- 16.4.4 Reversible Fault-Tolerant Normalization Register -- 16.4.5 Reversible Fault-Tolerant Parallel Adder -- 16.4.6 The Reversible Fault-Tolerant Division Circuit -- 16.5 Summary -- Chapter 17 Reversible Fault-Tolerant Decoder Circuit -- 17.1 Transistor Realization of Some Popular Reversible Gates -- 17.1.1 Feynman Double Gate -- 17.1.2 Fredkin Gate -- 17.2 Reversible Fault-Tolerant Decoder -- 17.3 Summary -- Chapter 18 Reversible Fault-Tolerant Barrel Shifter -- 18.1 Properties of Barrel Shifters -- 18.2 Reversible Fault-Tolerant Unidirectional Logarithmic Rotators -- 18.3 Fault-Tolerant Unidirectional Logarithmic Logical Shifters -- 18.4 Summary -- Chapter 19 Reversible Fault-Tolerant Programmable Logic Devices -- 19.1 Reversible Fault-Tolerant Programmable Logic Array -- 19.1.1 The Design of RFTPLA -- 19.2 Reversible Fault-Tolerant Programmable Array Logic -- 19.2.1 The Design of AND Plane of RFTPAL -- 19.2.2 The Design of Ex-OR Plane of RFTPAL -- 19.3 Reversible Fault-Tolerant LUT-Based FPGA -- 19.3.1 Reversible Fault-Tolerant Gates -- 19.3.2 Proof of Fault-Tolerance Properties of the MSH and MSB Gates -- 19.3.3 Physical Implementation of the Gates -- 19.3.4 Reversible Fault-Tolerant D Latch, Master-Slave Flip-Flop and 4×1 Multiplexer 19.3.5 Reversible Fault-Tolerant n-Input Look-Up Table |
| ctrlnum | (ZDB-30-PQE)EBC6301548 (ZDB-30-PAD)EBC6301548 (ZDB-89-EBL)EBL6301548 (OCoLC)1203962948 (DE-599)BVBBV047441882 |
| dewey-full | 006.3842 |
| dewey-hundreds | 000 - Computer science, information, general works |
| dewey-ones | 006 - Special computer methods |
| dewey-raw | 006.3842 |
| dewey-search | 006.3842 |
| dewey-sort | 16.3842 |
| dewey-tens | 000 - Computer science, information, general works |
| discipline | Physik Biologie Informatik |
| discipline_str_mv | Physik Biologie Informatik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>11060nmm a2200481zc 4500</leader><controlfield tag="001">BV047441882</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20240220 </controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">210827s2021 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781119679363</subfield><subfield code="9">978-1-119-67936-3</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781119679431</subfield><subfield code="9">978-1-119-67943-1</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-30-PQE)EBC6301548</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-30-PAD)EBC6301548</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-89-EBL)EBL6301548</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1203962948</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV047441882</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">006.3842</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">PHY 821</subfield><subfield code="2">stub</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 200</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Babu, Hafiz Md. Hasan</subfield><subfield code="d">1966-</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)1217495320</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Reversible and DNA computing</subfield><subfield code="c">Hafiz Md. Hasan Babu</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Hoboken, NJ, USA ; Chichester, West Sussex, UK</subfield><subfield code="b">Wiley</subfield><subfield code="c">2021</subfield></datafield><datafield tag="264" ind1=" " ind2="4"><subfield code="c">© 2021</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (xl, 392 Seiten)</subfield><subfield code="b">Illustrationen, Diagramme</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Description based on publisher supplied metadata and other sources</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">Cover -- Title Page -- Copyright -- Contents -- List of Figures -- List of Tables -- About the Author -- Preface -- Acknowledgments -- Acronyms -- Introduction -- Part I Reversible Circuits -- An Overview About Reversible Circuits -- Chapter 1 Reversible Logic Synthesis -- 1.1 Reversible Logic -- 1.2 Reversible Function -- 1.3 Reversible Logic Gate -- 1.4 Garbage Outputs -- 1.5 Constant Inputs -- 1.6 Quantum Cost -- 1.7 Delay -- 1.8 Power -- 1.9 Area -- 1.10 Hardware Complexity -- 1.11 Quantum Gate Calculation Complexity -- 1.12 Fan-Out -- 1.13 Self-Reversible -- 1.14 Reversible Computation -- 1.15 Area -- 1.16 Design Constraints for Reversible Logic Circuits -- 1.17 Quantum Analysis of Different Reversible Logic Gates -- 1.17.1 Reversible NOT Gate (Feynman Gate) -- 1.17.2 Toffoli Gate -- 1.17.3 Fredkin Gate -- 1.17.4 Peres Gate -- 1.18 Summary -- Chapter 2 Reversible Adder and Subtractor Circuits -- 2.1 Reversible Multi-Operand n-Digit Decimal Adder -- 2.1.1 Full Adder -- 2.1.1.0 The FAG Gate -- 2.1.1.0 Reversible FAG Gate as Full Adder -- 2.1.2 Carry Skip Adder -- 2.1.2.1 Design of Carry Skip Adder -- 2.1.3 Carry Look-Ahead Adder -- 2.2 Reversible BCD Adders -- 2.2.1 Design Procedure of the Reversible BCD Adder -- 2.2.1.1 Properties of the Reversible BCD Adder -- 2.2.2 Design Procedure of the Reversible Carry Skip BCD Adder -- 2.2.2.1 Properties of the Reversible Carry Skip BCD Adder -- 2.3 Reversible BCD Subtractor -- 2.3.1 Carry Look-Ahead BCD Subtractor -- 2.3.2 Carry Skip BCD Subtractor -- 2.3.3 Design of Conventional Reversible BCD Subtractor -- 2.3.3.1 Reversible Nine's Complement -- 2.3.3.2 Reversible BCD Subtractor -- 2.3.3.3 Reversible Design of Carry Look-Ahead BCD Subtractor -- 2.3.3.4 Reversible Design of Carry Skip BCD Subtractor -- 2.4 Summary -- Chapter 3 Reversible Multiplier Circuit -- 3.1 Multiplication Using Booth's Recoding</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">3.2 Reversible Gates as Half Adders and Full Adders -- 3.3 Some Signed Reversible Multipliers -- 3.4 Design of Reversible Multiplier Circuit -- 3.4.1 Some Quantum Gates -- 3.4.2 Recoding Cell -- 3.4.3 Partial Product Generation Circuit -- 3.4.4 Multi-Operand Addition Circuit -- 3.4.5 Calculation of Area and Power of n×n Multiplier Circuit -- 3.5 Summary -- Chapter 4 Reversible Division Circuit -- 4.1 The Division Approaches -- 4.1.1 Restoring Division -- 4.1.2 Nonrestoring Division -- 4.2 Components of Division Circuit -- 4.2.1 Reversible MUX -- 4.2.2 Reversible Register -- 4.2.3 Reversible PIPO Left-Shift Register -- 4.2.4 Reversible Parallel Adder -- 4.3 The Design of Reversible Division Circuit -- 4.4 Summary -- Chapter 5 Reversible Binary Comparator -- 5.1 Design of Reversible n-Bit Comparator -- 5.1.1 BJS Gate -- 5.1.2 Reversible 1-Bit Comparator Circuit -- 5.1.3 Reversible MSB Comparator Circuit -- 5.1.4 Reversible Single-Bit Greater or Equal Comparator Cell -- 5.1.5 Reversible Single-Bit Less Than Comparator Cell -- 5.1.6 Reversible 2-Bit Comparator Circuit -- 5.1.7 Reversible n-Bit Comparator Circuit -- 5.2 Summary -- Chapter 6 Reversible Sequential Circuits -- 6.1 An Example of Design Methodology -- 6.2 The Design of Reversible Latches -- 6.2.1 The SR Latch -- 6.2.2 The D Latch -- 6.2.2.1 The D Latch with Outputs Q and Q‾ -- 6.2.2.2 The Negative Enable Reversible D Latch -- 6.2.3 T Latch -- 6.2.4 The JK Latch -- 6.3 The Design of Reversible Master-Slave Flip-Flops -- 6.4 The Design of Reversible Latch and the Master-Slave Flip-Flop with Asynchronous SET and RESET Capabilities -- 6.5 Summary -- Chapter 7 Reversible Counter, Decoder, and Encoder Circuits -- 7.1 Synthesis of Reversible Counter -- 7.1.1 Reversible T Flip-Flop -- 7.1.2 Reversible Clocked T Flip-Flop -- 7.1.3 Reversible Master-Slave T Flip-Flop</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">7.1.4 Reversible Asynchronous Counter -- 7.1.5 Reversible Synchronous Counter -- 7.2 Reversible Decoder -- 7.2.1 Reversible Encoder -- 7.3 Summary -- Chapter 8 Reversible Barrel Shifter and Shift Register -- 8.1 Design Procedure of Reversible Bidirectional Barrel Shifter -- 8.1.1 Reversible 3 × 3 Modified BJN Gate -- 8.1.2 Reversible 2's Complement Generator -- 8.1.3 Reversible Swap Condition Generator -- 8.1.4 Reversible Right Rotator -- 8.1.4.1 (4, 3) Reversible Right Rotator -- 8.1.4.2 Generalized Reversible Right Rotator -- 8.1.5 Reversible Bidirectional Barrel Shifter -- 8.2 Design Procedure of Reversible Shift Register -- 8.2.1 Reversible Flip-Flop -- 8.2.1.1 Reversible SISO Shift Register -- 8.2.1.2 Reversible SIPO Shift Register -- 8.2.1.3 Reversible PISO Shift Register -- 8.2.1.4 Reversible PIPO Shift Register -- 8.2.1.5 Reversible Universal Shift Register -- 8.3 Summary -- Chapter 9 Reversible Multiplexer and Demultiplexer with Other Logical Operations -- 9.1 Reversible Logic Gates -- 9.1.1 RG1 Gate -- 9.1.2 RG2 Gate -- 9.2 Designs of Reversible Multiplexer and Demultiplexer with Other Logical Operations -- 9.2.1 The R-I Gate -- 9.2.2 The R-II Gate -- 9.3 Summary -- Chapter 10 Reversible Programmable Logic Devices -- 10.1 Reversible FPGA -- 10.1.1 3×3 Reversible NH Gate -- 10.1.2 4 × 4 Reversible BSP Gate -- 10.1.3 4-to-1 Reversible Multiplexer -- 10.1.4 Reversible D Latch -- 10.1.5 Reversible Write-Enabled Master-Slave Flip-Flop -- 10.1.6 Reversible RAM -- 10.1.7 Design of Reversible FPGA -- 10.2 Reversible PLA -- 10.2.1 The Design Procedure -- 10.2.1.1 Delay Calculation of a Reversible PLA -- 10.2.1.2 Delay Calculation of AND Plane -- 10.2.1.3 Delay Calculation of Ex-OR Plane -- 10.2.1.4 Delay of Overall Design -- 10.3 Summary -- Chapter 11 Reversible RAM and Programmable ROM -- 11.1 Reversible RAM -- 11.1.1 3×3 Reversible FS Gate</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">11.1.2 Reversible Decoder -- 11.1.3 Reversible D Flip-Flop -- 11.1.4 Reversible Write-Enabled Master-Slave D Flip-Flop -- 11.1.5 Reversible Random Access Memory -- 11.2 Reversible PROM -- 11.2.1 Reversible Decoder -- 11.2.2 Design of Reversible PROM -- 11.3 Summary -- Chapter 12 Reversible Arithmetic Logic Unit -- 12.1 Design of ALU -- 12.1.1 Conventional ALU -- 12.1.2 The ALU Based on Reversible Logic -- 12.1.2.1 The Reversible Function Generator -- 12.1.2.2 The Reversible Control Unit -- 12.2 Design of Reversible ALU -- 12.3 Summary -- Chapter 13 Reversible Control Unit -- 13.1 An Example of Control Unit -- 13.2 Different Components of a Control Unit -- 13.2.1 Reversible HL Gate -- 13.2.2 Reversible BJ Gate -- 13.2.3 Reversible 2-to-4 Decoder -- 13.2.4 Reversible 3-to-8 Decoder -- 13.2.5 Reversible n-to-2n Decoder -- 13.2.6 Reversible JK Flip-Flop -- 13.2.7 Reversible Sequence Counter -- 13.2.8 Reversible Instruction Register -- 13.2.9 Control of Registers and Memory -- 13.2.10 Construction Procedure and Complexities of the Control Unit -- 13.3 Summary -- Part II Reversible Fault Tolerance -- An Overview About Fault-Tolerance and Testable Circuits -- Chapter 14 Reversible Fault-Tolerant Adder Circuits -- 14.1 Properties of Fault Tolerance -- 14.1.1 Parity-Preserving Reversible Gates -- 14.2 Reversible Parity-Preserving Adders -- 14.2.1 Fault-Tolerant Full Adder -- 14.2.2 Fault-Tolerant Carry Skip Adder -- 14.2.3 Fault-Tolerant Carry Look-Ahead Adder -- 14.2.4 Fault-Tolerant Ripple Carry Adder -- 14.3 Summary -- Chapter 15 Reversible Fault-Tolerant Multiplier Circuit -- 15.1 Reversible Fault-Tolerant Multipliers -- 15.1.1 Reversible Fault-Tolerant n×n Multiplier -- 15.1.2 LMH Gate -- 15.1.3 Partial Product Generation -- 15.1.4 Multi-Operand Addition -- 15.2 Summary -- Chapter 16 Reversible Fault-Tolerant Division Circuit</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">16.1 Preliminaries of Division Circuits -- 16.1.1 Division Algorithms -- 16.2 The Division Method -- 16.2.1 Floating-Point Data and Rounding -- 16.2.2 Correctly Rounded Division -- 16.2.3 Correct Rounding from One-Sided Approximations -- 16.2.4 The Algorithm for Division Operation -- 16.3 Components of a Division Circuit -- 16.3.1 Reversible Fault-Tolerant MUX -- 16.3.2 Reversible Fault-Tolerant D Latch -- 16.4 The Design of the Division Circuit -- 16.4.1 Reversible Fault-Tolerant PIPO Left‐Shift Register -- 16.4.2 Reversible Fault-Tolerant Register -- 16.4.3 Reversible Fault-Tolerant Rounding Register -- 16.4.4 Reversible Fault-Tolerant Normalization Register -- 16.4.5 Reversible Fault-Tolerant Parallel Adder -- 16.4.6 The Reversible Fault-Tolerant Division Circuit -- 16.5 Summary -- Chapter 17 Reversible Fault-Tolerant Decoder Circuit -- 17.1 Transistor Realization of Some Popular Reversible Gates -- 17.1.1 Feynman Double Gate -- 17.1.2 Fredkin Gate -- 17.2 Reversible Fault-Tolerant Decoder -- 17.3 Summary -- Chapter 18 Reversible Fault-Tolerant Barrel Shifter -- 18.1 Properties of Barrel Shifters -- 18.2 Reversible Fault-Tolerant Unidirectional Logarithmic Rotators -- 18.3 Fault-Tolerant Unidirectional Logarithmic Logical Shifters -- 18.4 Summary -- Chapter 19 Reversible Fault-Tolerant Programmable Logic Devices -- 19.1 Reversible Fault-Tolerant Programmable Logic Array -- 19.1.1 The Design of RFTPLA -- 19.2 Reversible Fault-Tolerant Programmable Array Logic -- 19.2.1 The Design of AND Plane of RFTPAL -- 19.2.2 The Design of Ex-OR Plane of RFTPAL -- 19.3 Reversible Fault-Tolerant LUT-Based FPGA -- 19.3.1 Reversible Fault-Tolerant Gates -- 19.3.2 Proof of Fault-Tolerance Properties of the MSH and MSB Gates -- 19.3.3 Physical Implementation of the Gates -- 19.3.4 Reversible Fault-Tolerant D Latch, Master-Slave Flip-Flop and 4×1 Multiplexer</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">19.3.5 Reversible Fault-Tolerant n-Input Look-Up Table</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Molecular computers</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="a">Babu, Hafiz M, H</subfield><subfield code="t">Reversible and DNA Computing</subfield><subfield code="d">Newark : John Wiley & Sons, Incorporated,c2020</subfield><subfield code="n">Druck-Ausgabe, Hardcover</subfield><subfield code="z">978-1-119-67942-4</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-30-PQE</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-032844034</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://ebookcentral.proquest.com/lib/munchentech/detail.action?docID=6301548</subfield><subfield code="l">TUM01</subfield><subfield code="p">ZDB-30-PQE</subfield><subfield code="q">TUM_PDA_PQE_Kauf</subfield><subfield code="x">Aggregator</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV047441882 |
| illustrated | Not Illustrated |
| index_date | 2024-07-03T18:01:23Z |
| indexdate | 2024-07-10T09:12:16Z |
| institution | BVB |
| isbn | 9781119679363 9781119679431 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-032844034 |
| oclc_num | 1203962948 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM |
| owner_facet | DE-91 DE-BY-TUM |
| physical | 1 Online-Ressource (xl, 392 Seiten) Illustrationen, Diagramme |
| psigel | ZDB-30-PQE ZDB-30-PQE TUM_PDA_PQE_Kauf |
| publishDate | 2021 |
| publishDateSearch | 2021 |
| publishDateSort | 2021 |
| publisher | Wiley |
| record_format | marc |
| spelling | Babu, Hafiz Md. Hasan 1966- Verfasser (DE-588)1217495320 aut Reversible and DNA computing Hafiz Md. Hasan Babu Hoboken, NJ, USA ; Chichester, West Sussex, UK Wiley 2021 © 2021 1 Online-Ressource (xl, 392 Seiten) Illustrationen, Diagramme txt rdacontent c rdamedia cr rdacarrier Description based on publisher supplied metadata and other sources Cover -- Title Page -- Copyright -- Contents -- List of Figures -- List of Tables -- About the Author -- Preface -- Acknowledgments -- Acronyms -- Introduction -- Part I Reversible Circuits -- An Overview About Reversible Circuits -- Chapter 1 Reversible Logic Synthesis -- 1.1 Reversible Logic -- 1.2 Reversible Function -- 1.3 Reversible Logic Gate -- 1.4 Garbage Outputs -- 1.5 Constant Inputs -- 1.6 Quantum Cost -- 1.7 Delay -- 1.8 Power -- 1.9 Area -- 1.10 Hardware Complexity -- 1.11 Quantum Gate Calculation Complexity -- 1.12 Fan-Out -- 1.13 Self-Reversible -- 1.14 Reversible Computation -- 1.15 Area -- 1.16 Design Constraints for Reversible Logic Circuits -- 1.17 Quantum Analysis of Different Reversible Logic Gates -- 1.17.1 Reversible NOT Gate (Feynman Gate) -- 1.17.2 Toffoli Gate -- 1.17.3 Fredkin Gate -- 1.17.4 Peres Gate -- 1.18 Summary -- Chapter 2 Reversible Adder and Subtractor Circuits -- 2.1 Reversible Multi-Operand n-Digit Decimal Adder -- 2.1.1 Full Adder -- 2.1.1.0 The FAG Gate -- 2.1.1.0 Reversible FAG Gate as Full Adder -- 2.1.2 Carry Skip Adder -- 2.1.2.1 Design of Carry Skip Adder -- 2.1.3 Carry Look-Ahead Adder -- 2.2 Reversible BCD Adders -- 2.2.1 Design Procedure of the Reversible BCD Adder -- 2.2.1.1 Properties of the Reversible BCD Adder -- 2.2.2 Design Procedure of the Reversible Carry Skip BCD Adder -- 2.2.2.1 Properties of the Reversible Carry Skip BCD Adder -- 2.3 Reversible BCD Subtractor -- 2.3.1 Carry Look-Ahead BCD Subtractor -- 2.3.2 Carry Skip BCD Subtractor -- 2.3.3 Design of Conventional Reversible BCD Subtractor -- 2.3.3.1 Reversible Nine's Complement -- 2.3.3.2 Reversible BCD Subtractor -- 2.3.3.3 Reversible Design of Carry Look-Ahead BCD Subtractor -- 2.3.3.4 Reversible Design of Carry Skip BCD Subtractor -- 2.4 Summary -- Chapter 3 Reversible Multiplier Circuit -- 3.1 Multiplication Using Booth's Recoding 3.2 Reversible Gates as Half Adders and Full Adders -- 3.3 Some Signed Reversible Multipliers -- 3.4 Design of Reversible Multiplier Circuit -- 3.4.1 Some Quantum Gates -- 3.4.2 Recoding Cell -- 3.4.3 Partial Product Generation Circuit -- 3.4.4 Multi-Operand Addition Circuit -- 3.4.5 Calculation of Area and Power of n×n Multiplier Circuit -- 3.5 Summary -- Chapter 4 Reversible Division Circuit -- 4.1 The Division Approaches -- 4.1.1 Restoring Division -- 4.1.2 Nonrestoring Division -- 4.2 Components of Division Circuit -- 4.2.1 Reversible MUX -- 4.2.2 Reversible Register -- 4.2.3 Reversible PIPO Left-Shift Register -- 4.2.4 Reversible Parallel Adder -- 4.3 The Design of Reversible Division Circuit -- 4.4 Summary -- Chapter 5 Reversible Binary Comparator -- 5.1 Design of Reversible n-Bit Comparator -- 5.1.1 BJS Gate -- 5.1.2 Reversible 1-Bit Comparator Circuit -- 5.1.3 Reversible MSB Comparator Circuit -- 5.1.4 Reversible Single-Bit Greater or Equal Comparator Cell -- 5.1.5 Reversible Single-Bit Less Than Comparator Cell -- 5.1.6 Reversible 2-Bit Comparator Circuit -- 5.1.7 Reversible n-Bit Comparator Circuit -- 5.2 Summary -- Chapter 6 Reversible Sequential Circuits -- 6.1 An Example of Design Methodology -- 6.2 The Design of Reversible Latches -- 6.2.1 The SR Latch -- 6.2.2 The D Latch -- 6.2.2.1 The D Latch with Outputs Q and Q‾ -- 6.2.2.2 The Negative Enable Reversible D Latch -- 6.2.3 T Latch -- 6.2.4 The JK Latch -- 6.3 The Design of Reversible Master-Slave Flip-Flops -- 6.4 The Design of Reversible Latch and the Master-Slave Flip-Flop with Asynchronous SET and RESET Capabilities -- 6.5 Summary -- Chapter 7 Reversible Counter, Decoder, and Encoder Circuits -- 7.1 Synthesis of Reversible Counter -- 7.1.1 Reversible T Flip-Flop -- 7.1.2 Reversible Clocked T Flip-Flop -- 7.1.3 Reversible Master-Slave T Flip-Flop 7.1.4 Reversible Asynchronous Counter -- 7.1.5 Reversible Synchronous Counter -- 7.2 Reversible Decoder -- 7.2.1 Reversible Encoder -- 7.3 Summary -- Chapter 8 Reversible Barrel Shifter and Shift Register -- 8.1 Design Procedure of Reversible Bidirectional Barrel Shifter -- 8.1.1 Reversible 3 × 3 Modified BJN Gate -- 8.1.2 Reversible 2's Complement Generator -- 8.1.3 Reversible Swap Condition Generator -- 8.1.4 Reversible Right Rotator -- 8.1.4.1 (4, 3) Reversible Right Rotator -- 8.1.4.2 Generalized Reversible Right Rotator -- 8.1.5 Reversible Bidirectional Barrel Shifter -- 8.2 Design Procedure of Reversible Shift Register -- 8.2.1 Reversible Flip-Flop -- 8.2.1.1 Reversible SISO Shift Register -- 8.2.1.2 Reversible SIPO Shift Register -- 8.2.1.3 Reversible PISO Shift Register -- 8.2.1.4 Reversible PIPO Shift Register -- 8.2.1.5 Reversible Universal Shift Register -- 8.3 Summary -- Chapter 9 Reversible Multiplexer and Demultiplexer with Other Logical Operations -- 9.1 Reversible Logic Gates -- 9.1.1 RG1 Gate -- 9.1.2 RG2 Gate -- 9.2 Designs of Reversible Multiplexer and Demultiplexer with Other Logical Operations -- 9.2.1 The R-I Gate -- 9.2.2 The R-II Gate -- 9.3 Summary -- Chapter 10 Reversible Programmable Logic Devices -- 10.1 Reversible FPGA -- 10.1.1 3×3 Reversible NH Gate -- 10.1.2 4 × 4 Reversible BSP Gate -- 10.1.3 4-to-1 Reversible Multiplexer -- 10.1.4 Reversible D Latch -- 10.1.5 Reversible Write-Enabled Master-Slave Flip-Flop -- 10.1.6 Reversible RAM -- 10.1.7 Design of Reversible FPGA -- 10.2 Reversible PLA -- 10.2.1 The Design Procedure -- 10.2.1.1 Delay Calculation of a Reversible PLA -- 10.2.1.2 Delay Calculation of AND Plane -- 10.2.1.3 Delay Calculation of Ex-OR Plane -- 10.2.1.4 Delay of Overall Design -- 10.3 Summary -- Chapter 11 Reversible RAM and Programmable ROM -- 11.1 Reversible RAM -- 11.1.1 3×3 Reversible FS Gate 11.1.2 Reversible Decoder -- 11.1.3 Reversible D Flip-Flop -- 11.1.4 Reversible Write-Enabled Master-Slave D Flip-Flop -- 11.1.5 Reversible Random Access Memory -- 11.2 Reversible PROM -- 11.2.1 Reversible Decoder -- 11.2.2 Design of Reversible PROM -- 11.3 Summary -- Chapter 12 Reversible Arithmetic Logic Unit -- 12.1 Design of ALU -- 12.1.1 Conventional ALU -- 12.1.2 The ALU Based on Reversible Logic -- 12.1.2.1 The Reversible Function Generator -- 12.1.2.2 The Reversible Control Unit -- 12.2 Design of Reversible ALU -- 12.3 Summary -- Chapter 13 Reversible Control Unit -- 13.1 An Example of Control Unit -- 13.2 Different Components of a Control Unit -- 13.2.1 Reversible HL Gate -- 13.2.2 Reversible BJ Gate -- 13.2.3 Reversible 2-to-4 Decoder -- 13.2.4 Reversible 3-to-8 Decoder -- 13.2.5 Reversible n-to-2n Decoder -- 13.2.6 Reversible JK Flip-Flop -- 13.2.7 Reversible Sequence Counter -- 13.2.8 Reversible Instruction Register -- 13.2.9 Control of Registers and Memory -- 13.2.10 Construction Procedure and Complexities of the Control Unit -- 13.3 Summary -- Part II Reversible Fault Tolerance -- An Overview About Fault-Tolerance and Testable Circuits -- Chapter 14 Reversible Fault-Tolerant Adder Circuits -- 14.1 Properties of Fault Tolerance -- 14.1.1 Parity-Preserving Reversible Gates -- 14.2 Reversible Parity-Preserving Adders -- 14.2.1 Fault-Tolerant Full Adder -- 14.2.2 Fault-Tolerant Carry Skip Adder -- 14.2.3 Fault-Tolerant Carry Look-Ahead Adder -- 14.2.4 Fault-Tolerant Ripple Carry Adder -- 14.3 Summary -- Chapter 15 Reversible Fault-Tolerant Multiplier Circuit -- 15.1 Reversible Fault-Tolerant Multipliers -- 15.1.1 Reversible Fault-Tolerant n×n Multiplier -- 15.1.2 LMH Gate -- 15.1.3 Partial Product Generation -- 15.1.4 Multi-Operand Addition -- 15.2 Summary -- Chapter 16 Reversible Fault-Tolerant Division Circuit 16.1 Preliminaries of Division Circuits -- 16.1.1 Division Algorithms -- 16.2 The Division Method -- 16.2.1 Floating-Point Data and Rounding -- 16.2.2 Correctly Rounded Division -- 16.2.3 Correct Rounding from One-Sided Approximations -- 16.2.4 The Algorithm for Division Operation -- 16.3 Components of a Division Circuit -- 16.3.1 Reversible Fault-Tolerant MUX -- 16.3.2 Reversible Fault-Tolerant D Latch -- 16.4 The Design of the Division Circuit -- 16.4.1 Reversible Fault-Tolerant PIPO Left‐Shift Register -- 16.4.2 Reversible Fault-Tolerant Register -- 16.4.3 Reversible Fault-Tolerant Rounding Register -- 16.4.4 Reversible Fault-Tolerant Normalization Register -- 16.4.5 Reversible Fault-Tolerant Parallel Adder -- 16.4.6 The Reversible Fault-Tolerant Division Circuit -- 16.5 Summary -- Chapter 17 Reversible Fault-Tolerant Decoder Circuit -- 17.1 Transistor Realization of Some Popular Reversible Gates -- 17.1.1 Feynman Double Gate -- 17.1.2 Fredkin Gate -- 17.2 Reversible Fault-Tolerant Decoder -- 17.3 Summary -- Chapter 18 Reversible Fault-Tolerant Barrel Shifter -- 18.1 Properties of Barrel Shifters -- 18.2 Reversible Fault-Tolerant Unidirectional Logarithmic Rotators -- 18.3 Fault-Tolerant Unidirectional Logarithmic Logical Shifters -- 18.4 Summary -- Chapter 19 Reversible Fault-Tolerant Programmable Logic Devices -- 19.1 Reversible Fault-Tolerant Programmable Logic Array -- 19.1.1 The Design of RFTPLA -- 19.2 Reversible Fault-Tolerant Programmable Array Logic -- 19.2.1 The Design of AND Plane of RFTPAL -- 19.2.2 The Design of Ex-OR Plane of RFTPAL -- 19.3 Reversible Fault-Tolerant LUT-Based FPGA -- 19.3.1 Reversible Fault-Tolerant Gates -- 19.3.2 Proof of Fault-Tolerance Properties of the MSH and MSB Gates -- 19.3.3 Physical Implementation of the Gates -- 19.3.4 Reversible Fault-Tolerant D Latch, Master-Slave Flip-Flop and 4×1 Multiplexer 19.3.5 Reversible Fault-Tolerant n-Input Look-Up Table Molecular computers Erscheint auch als Babu, Hafiz M, H Reversible and DNA Computing Newark : John Wiley & Sons, Incorporated,c2020 Druck-Ausgabe, Hardcover 978-1-119-67942-4 |
| spellingShingle | Babu, Hafiz Md. Hasan 1966- Reversible and DNA computing Cover -- Title Page -- Copyright -- Contents -- List of Figures -- List of Tables -- About the Author -- Preface -- Acknowledgments -- Acronyms -- Introduction -- Part I Reversible Circuits -- An Overview About Reversible Circuits -- Chapter 1 Reversible Logic Synthesis -- 1.1 Reversible Logic -- 1.2 Reversible Function -- 1.3 Reversible Logic Gate -- 1.4 Garbage Outputs -- 1.5 Constant Inputs -- 1.6 Quantum Cost -- 1.7 Delay -- 1.8 Power -- 1.9 Area -- 1.10 Hardware Complexity -- 1.11 Quantum Gate Calculation Complexity -- 1.12 Fan-Out -- 1.13 Self-Reversible -- 1.14 Reversible Computation -- 1.15 Area -- 1.16 Design Constraints for Reversible Logic Circuits -- 1.17 Quantum Analysis of Different Reversible Logic Gates -- 1.17.1 Reversible NOT Gate (Feynman Gate) -- 1.17.2 Toffoli Gate -- 1.17.3 Fredkin Gate -- 1.17.4 Peres Gate -- 1.18 Summary -- Chapter 2 Reversible Adder and Subtractor Circuits -- 2.1 Reversible Multi-Operand n-Digit Decimal Adder -- 2.1.1 Full Adder -- 2.1.1.0 The FAG Gate -- 2.1.1.0 Reversible FAG Gate as Full Adder -- 2.1.2 Carry Skip Adder -- 2.1.2.1 Design of Carry Skip Adder -- 2.1.3 Carry Look-Ahead Adder -- 2.2 Reversible BCD Adders -- 2.2.1 Design Procedure of the Reversible BCD Adder -- 2.2.1.1 Properties of the Reversible BCD Adder -- 2.2.2 Design Procedure of the Reversible Carry Skip BCD Adder -- 2.2.2.1 Properties of the Reversible Carry Skip BCD Adder -- 2.3 Reversible BCD Subtractor -- 2.3.1 Carry Look-Ahead BCD Subtractor -- 2.3.2 Carry Skip BCD Subtractor -- 2.3.3 Design of Conventional Reversible BCD Subtractor -- 2.3.3.1 Reversible Nine's Complement -- 2.3.3.2 Reversible BCD Subtractor -- 2.3.3.3 Reversible Design of Carry Look-Ahead BCD Subtractor -- 2.3.3.4 Reversible Design of Carry Skip BCD Subtractor -- 2.4 Summary -- Chapter 3 Reversible Multiplier Circuit -- 3.1 Multiplication Using Booth's Recoding 3.2 Reversible Gates as Half Adders and Full Adders -- 3.3 Some Signed Reversible Multipliers -- 3.4 Design of Reversible Multiplier Circuit -- 3.4.1 Some Quantum Gates -- 3.4.2 Recoding Cell -- 3.4.3 Partial Product Generation Circuit -- 3.4.4 Multi-Operand Addition Circuit -- 3.4.5 Calculation of Area and Power of n×n Multiplier Circuit -- 3.5 Summary -- Chapter 4 Reversible Division Circuit -- 4.1 The Division Approaches -- 4.1.1 Restoring Division -- 4.1.2 Nonrestoring Division -- 4.2 Components of Division Circuit -- 4.2.1 Reversible MUX -- 4.2.2 Reversible Register -- 4.2.3 Reversible PIPO Left-Shift Register -- 4.2.4 Reversible Parallel Adder -- 4.3 The Design of Reversible Division Circuit -- 4.4 Summary -- Chapter 5 Reversible Binary Comparator -- 5.1 Design of Reversible n-Bit Comparator -- 5.1.1 BJS Gate -- 5.1.2 Reversible 1-Bit Comparator Circuit -- 5.1.3 Reversible MSB Comparator Circuit -- 5.1.4 Reversible Single-Bit Greater or Equal Comparator Cell -- 5.1.5 Reversible Single-Bit Less Than Comparator Cell -- 5.1.6 Reversible 2-Bit Comparator Circuit -- 5.1.7 Reversible n-Bit Comparator Circuit -- 5.2 Summary -- Chapter 6 Reversible Sequential Circuits -- 6.1 An Example of Design Methodology -- 6.2 The Design of Reversible Latches -- 6.2.1 The SR Latch -- 6.2.2 The D Latch -- 6.2.2.1 The D Latch with Outputs Q and Q‾ -- 6.2.2.2 The Negative Enable Reversible D Latch -- 6.2.3 T Latch -- 6.2.4 The JK Latch -- 6.3 The Design of Reversible Master-Slave Flip-Flops -- 6.4 The Design of Reversible Latch and the Master-Slave Flip-Flop with Asynchronous SET and RESET Capabilities -- 6.5 Summary -- Chapter 7 Reversible Counter, Decoder, and Encoder Circuits -- 7.1 Synthesis of Reversible Counter -- 7.1.1 Reversible T Flip-Flop -- 7.1.2 Reversible Clocked T Flip-Flop -- 7.1.3 Reversible Master-Slave T Flip-Flop 7.1.4 Reversible Asynchronous Counter -- 7.1.5 Reversible Synchronous Counter -- 7.2 Reversible Decoder -- 7.2.1 Reversible Encoder -- 7.3 Summary -- Chapter 8 Reversible Barrel Shifter and Shift Register -- 8.1 Design Procedure of Reversible Bidirectional Barrel Shifter -- 8.1.1 Reversible 3 × 3 Modified BJN Gate -- 8.1.2 Reversible 2's Complement Generator -- 8.1.3 Reversible Swap Condition Generator -- 8.1.4 Reversible Right Rotator -- 8.1.4.1 (4, 3) Reversible Right Rotator -- 8.1.4.2 Generalized Reversible Right Rotator -- 8.1.5 Reversible Bidirectional Barrel Shifter -- 8.2 Design Procedure of Reversible Shift Register -- 8.2.1 Reversible Flip-Flop -- 8.2.1.1 Reversible SISO Shift Register -- 8.2.1.2 Reversible SIPO Shift Register -- 8.2.1.3 Reversible PISO Shift Register -- 8.2.1.4 Reversible PIPO Shift Register -- 8.2.1.5 Reversible Universal Shift Register -- 8.3 Summary -- Chapter 9 Reversible Multiplexer and Demultiplexer with Other Logical Operations -- 9.1 Reversible Logic Gates -- 9.1.1 RG1 Gate -- 9.1.2 RG2 Gate -- 9.2 Designs of Reversible Multiplexer and Demultiplexer with Other Logical Operations -- 9.2.1 The R-I Gate -- 9.2.2 The R-II Gate -- 9.3 Summary -- Chapter 10 Reversible Programmable Logic Devices -- 10.1 Reversible FPGA -- 10.1.1 3×3 Reversible NH Gate -- 10.1.2 4 × 4 Reversible BSP Gate -- 10.1.3 4-to-1 Reversible Multiplexer -- 10.1.4 Reversible D Latch -- 10.1.5 Reversible Write-Enabled Master-Slave Flip-Flop -- 10.1.6 Reversible RAM -- 10.1.7 Design of Reversible FPGA -- 10.2 Reversible PLA -- 10.2.1 The Design Procedure -- 10.2.1.1 Delay Calculation of a Reversible PLA -- 10.2.1.2 Delay Calculation of AND Plane -- 10.2.1.3 Delay Calculation of Ex-OR Plane -- 10.2.1.4 Delay of Overall Design -- 10.3 Summary -- Chapter 11 Reversible RAM and Programmable ROM -- 11.1 Reversible RAM -- 11.1.1 3×3 Reversible FS Gate 11.1.2 Reversible Decoder -- 11.1.3 Reversible D Flip-Flop -- 11.1.4 Reversible Write-Enabled Master-Slave D Flip-Flop -- 11.1.5 Reversible Random Access Memory -- 11.2 Reversible PROM -- 11.2.1 Reversible Decoder -- 11.2.2 Design of Reversible PROM -- 11.3 Summary -- Chapter 12 Reversible Arithmetic Logic Unit -- 12.1 Design of ALU -- 12.1.1 Conventional ALU -- 12.1.2 The ALU Based on Reversible Logic -- 12.1.2.1 The Reversible Function Generator -- 12.1.2.2 The Reversible Control Unit -- 12.2 Design of Reversible ALU -- 12.3 Summary -- Chapter 13 Reversible Control Unit -- 13.1 An Example of Control Unit -- 13.2 Different Components of a Control Unit -- 13.2.1 Reversible HL Gate -- 13.2.2 Reversible BJ Gate -- 13.2.3 Reversible 2-to-4 Decoder -- 13.2.4 Reversible 3-to-8 Decoder -- 13.2.5 Reversible n-to-2n Decoder -- 13.2.6 Reversible JK Flip-Flop -- 13.2.7 Reversible Sequence Counter -- 13.2.8 Reversible Instruction Register -- 13.2.9 Control of Registers and Memory -- 13.2.10 Construction Procedure and Complexities of the Control Unit -- 13.3 Summary -- Part II Reversible Fault Tolerance -- An Overview About Fault-Tolerance and Testable Circuits -- Chapter 14 Reversible Fault-Tolerant Adder Circuits -- 14.1 Properties of Fault Tolerance -- 14.1.1 Parity-Preserving Reversible Gates -- 14.2 Reversible Parity-Preserving Adders -- 14.2.1 Fault-Tolerant Full Adder -- 14.2.2 Fault-Tolerant Carry Skip Adder -- 14.2.3 Fault-Tolerant Carry Look-Ahead Adder -- 14.2.4 Fault-Tolerant Ripple Carry Adder -- 14.3 Summary -- Chapter 15 Reversible Fault-Tolerant Multiplier Circuit -- 15.1 Reversible Fault-Tolerant Multipliers -- 15.1.1 Reversible Fault-Tolerant n×n Multiplier -- 15.1.2 LMH Gate -- 15.1.3 Partial Product Generation -- 15.1.4 Multi-Operand Addition -- 15.2 Summary -- Chapter 16 Reversible Fault-Tolerant Division Circuit 16.1 Preliminaries of Division Circuits -- 16.1.1 Division Algorithms -- 16.2 The Division Method -- 16.2.1 Floating-Point Data and Rounding -- 16.2.2 Correctly Rounded Division -- 16.2.3 Correct Rounding from One-Sided Approximations -- 16.2.4 The Algorithm for Division Operation -- 16.3 Components of a Division Circuit -- 16.3.1 Reversible Fault-Tolerant MUX -- 16.3.2 Reversible Fault-Tolerant D Latch -- 16.4 The Design of the Division Circuit -- 16.4.1 Reversible Fault-Tolerant PIPO Left‐Shift Register -- 16.4.2 Reversible Fault-Tolerant Register -- 16.4.3 Reversible Fault-Tolerant Rounding Register -- 16.4.4 Reversible Fault-Tolerant Normalization Register -- 16.4.5 Reversible Fault-Tolerant Parallel Adder -- 16.4.6 The Reversible Fault-Tolerant Division Circuit -- 16.5 Summary -- Chapter 17 Reversible Fault-Tolerant Decoder Circuit -- 17.1 Transistor Realization of Some Popular Reversible Gates -- 17.1.1 Feynman Double Gate -- 17.1.2 Fredkin Gate -- 17.2 Reversible Fault-Tolerant Decoder -- 17.3 Summary -- Chapter 18 Reversible Fault-Tolerant Barrel Shifter -- 18.1 Properties of Barrel Shifters -- 18.2 Reversible Fault-Tolerant Unidirectional Logarithmic Rotators -- 18.3 Fault-Tolerant Unidirectional Logarithmic Logical Shifters -- 18.4 Summary -- Chapter 19 Reversible Fault-Tolerant Programmable Logic Devices -- 19.1 Reversible Fault-Tolerant Programmable Logic Array -- 19.1.1 The Design of RFTPLA -- 19.2 Reversible Fault-Tolerant Programmable Array Logic -- 19.2.1 The Design of AND Plane of RFTPAL -- 19.2.2 The Design of Ex-OR Plane of RFTPAL -- 19.3 Reversible Fault-Tolerant LUT-Based FPGA -- 19.3.1 Reversible Fault-Tolerant Gates -- 19.3.2 Proof of Fault-Tolerance Properties of the MSH and MSB Gates -- 19.3.3 Physical Implementation of the Gates -- 19.3.4 Reversible Fault-Tolerant D Latch, Master-Slave Flip-Flop and 4×1 Multiplexer 19.3.5 Reversible Fault-Tolerant n-Input Look-Up Table Molecular computers |
| title | Reversible and DNA computing |
| title_auth | Reversible and DNA computing |
| title_exact_search | Reversible and DNA computing |
| title_exact_search_txtP | Reversible and DNA computing |
| title_full | Reversible and DNA computing Hafiz Md. Hasan Babu |
| title_fullStr | Reversible and DNA computing Hafiz Md. Hasan Babu |
| title_full_unstemmed | Reversible and DNA computing Hafiz Md. Hasan Babu |
| title_short | Reversible and DNA computing |
| title_sort | reversible and dna computing |
| topic | Molecular computers |
| topic_facet | Molecular computers |
| work_keys_str_mv | AT babuhafizmdhasan reversibleanddnacomputing |