Advanced VLSI design and testability issues:
Gespeichert in:
| Weitere Verfasser: | , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boca Raton ; London ; New York
CRC Press
2020
|
| Schlagworte: | |
| Online-Zugang: | Volltext |
| Beschreibung: | Description based on publisher supplied metadata and other sources |
| Beschreibung: | 1 Online-Ressource (404 Seiten) |
| ISBN: | 9781003083436 9781000168174 |
| DOI: | 10.1201/9781003083436 |
Internformat
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| 245 | 1 | 0 | |a Advanced VLSI design and testability issues |c edited bySuman Lata Tripathi, Sobhit Saxena, and Sushanta Kumar Mohapatra |
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| 505 | 8 | |a Intro -- Half Title -- Title Page -- Copyright Page -- Table of Contents -- Preface to the First Edition -- Editors -- Contributors -- Chapter 1 Digital Design with Programmable Logic Devices -- Chapter 2 Review of Digital Electronics Design -- Chapter 3 Verilog HDL for Digital and Analog Design -- Chapter 4 Introduction to Hardware Description Languages -- Chapter 5 Introduction to Hardware Description Languages (HDLs) -- Chapter 6 Emerging Trends in Nanoscale Semiconductor Devices -- Chapter 7 Design Challenges and Solutions in CMOS-Based FET -- Chapter 8 Analytical Design of FET-Based Biosensors -- Chapter 9 Low-Power FET-Based Biosensors -- Chapter 10 Nanowire Array-Based Gate-All-Around MOSFET for Next-Generation Memory Devices -- Chapter 11 Design of 7T SRAM Cell Using FinFET Technology -- Chapter 12 Performance Analysis of AlGaN/GaN Heterostructure Field-Effect Transistor (HFET) -- Chapter 13 Synthesis of Polymer-Based Composites for Application in Field-Effect Transistors -- Chapter 14 Power Efficiency Analysis of Low-Power Circuit Design Techniques in 90-nm CMOS Technology -- Chapter 15 Macromodeling and Synthesis of Analog Circuits -- Chapter 16 Performance-Linked Phase-Locked Loop Architectures: Recent Developments -- Chapter 17 Review of Analog-to-Digital and Digital-to-Analog Converters for A Smart Antenna Application -- Chapter 18 Active Inductor-Based VCO for Wireless Communication -- Chapter 19 Fault Simulation Algorithms: Verilog Implementation -- Chapter 20 Hardware Protection through Logic Obfuscation -- Index | |
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| 700 | 1 | |a Saxena, Sobhit |4 edt | |
| 700 | 1 | |a Mohapatra, Sushanta Kumar |4 edt | |
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Datensatz im Suchindex
| _version_ | 1804182734573142016 |
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| author2 | Tripathi, Suman Lata Saxena, Sobhit Mohapatra, Sushanta Kumar |
| author2_role | edt edt edt |
| author2_variant | s l t sl slt s s ss s k m sk skm |
| author_GND | (DE-588)1240855079 |
| author_facet | Tripathi, Suman Lata Saxena, Sobhit Mohapatra, Sushanta Kumar |
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| contents | Intro -- Half Title -- Title Page -- Copyright Page -- Table of Contents -- Preface to the First Edition -- Editors -- Contributors -- Chapter 1 Digital Design with Programmable Logic Devices -- Chapter 2 Review of Digital Electronics Design -- Chapter 3 Verilog HDL for Digital and Analog Design -- Chapter 4 Introduction to Hardware Description Languages -- Chapter 5 Introduction to Hardware Description Languages (HDLs) -- Chapter 6 Emerging Trends in Nanoscale Semiconductor Devices -- Chapter 7 Design Challenges and Solutions in CMOS-Based FET -- Chapter 8 Analytical Design of FET-Based Biosensors -- Chapter 9 Low-Power FET-Based Biosensors -- Chapter 10 Nanowire Array-Based Gate-All-Around MOSFET for Next-Generation Memory Devices -- Chapter 11 Design of 7T SRAM Cell Using FinFET Technology -- Chapter 12 Performance Analysis of AlGaN/GaN Heterostructure Field-Effect Transistor (HFET) -- Chapter 13 Synthesis of Polymer-Based Composites for Application in Field-Effect Transistors -- Chapter 14 Power Efficiency Analysis of Low-Power Circuit Design Techniques in 90-nm CMOS Technology -- Chapter 15 Macromodeling and Synthesis of Analog Circuits -- Chapter 16 Performance-Linked Phase-Locked Loop Architectures: Recent Developments -- Chapter 17 Review of Analog-to-Digital and Digital-to-Analog Converters for A Smart Antenna Application -- Chapter 18 Active Inductor-Based VCO for Wireless Communication -- Chapter 19 Fault Simulation Algorithms: Verilog Implementation -- Chapter 20 Hardware Protection through Logic Obfuscation -- Index |
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| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1201/9781003083436 |
| format | Electronic eBook |
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| isbn | 9781003083436 9781000168174 |
| language | English |
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| spelling | Advanced VLSI design and testability issues edited bySuman Lata Tripathi, Sobhit Saxena, and Sushanta Kumar Mohapatra Boca Raton ; London ; New York CRC Press 2020 ©2021 1 Online-Ressource (404 Seiten) txt rdacontent c rdamedia cr rdacarrier Description based on publisher supplied metadata and other sources Intro -- Half Title -- Title Page -- Copyright Page -- Table of Contents -- Preface to the First Edition -- Editors -- Contributors -- Chapter 1 Digital Design with Programmable Logic Devices -- Chapter 2 Review of Digital Electronics Design -- Chapter 3 Verilog HDL for Digital and Analog Design -- Chapter 4 Introduction to Hardware Description Languages -- Chapter 5 Introduction to Hardware Description Languages (HDLs) -- Chapter 6 Emerging Trends in Nanoscale Semiconductor Devices -- Chapter 7 Design Challenges and Solutions in CMOS-Based FET -- Chapter 8 Analytical Design of FET-Based Biosensors -- Chapter 9 Low-Power FET-Based Biosensors -- Chapter 10 Nanowire Array-Based Gate-All-Around MOSFET for Next-Generation Memory Devices -- Chapter 11 Design of 7T SRAM Cell Using FinFET Technology -- Chapter 12 Performance Analysis of AlGaN/GaN Heterostructure Field-Effect Transistor (HFET) -- Chapter 13 Synthesis of Polymer-Based Composites for Application in Field-Effect Transistors -- Chapter 14 Power Efficiency Analysis of Low-Power Circuit Design Techniques in 90-nm CMOS Technology -- Chapter 15 Macromodeling and Synthesis of Analog Circuits -- Chapter 16 Performance-Linked Phase-Locked Loop Architectures: Recent Developments -- Chapter 17 Review of Analog-to-Digital and Digital-to-Analog Converters for A Smart Antenna Application -- Chapter 18 Active Inductor-Based VCO for Wireless Communication -- Chapter 19 Fault Simulation Algorithms: Verilog Implementation -- Chapter 20 Hardware Protection through Logic Obfuscation -- Index Integrated circuits-Very large scale integration-Design and construction VLSI (DE-588)4117388-0 gnd rswk-swf VLSI (DE-588)4117388-0 s DE-604 Tripathi, Suman Lata (DE-588)1240855079 edt Saxena, Sobhit edt Mohapatra, Sushanta Kumar edt Erscheint auch als Druck-Ausgabe Tripathi, Suman Lata Advanced VLSI Design and Testability Issues Milton : Taylor & Francis Group,c2020 978-0-367-49282-3 https://doi.org/10.1201/9781003083436 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Advanced VLSI design and testability issues Intro -- Half Title -- Title Page -- Copyright Page -- Table of Contents -- Preface to the First Edition -- Editors -- Contributors -- Chapter 1 Digital Design with Programmable Logic Devices -- Chapter 2 Review of Digital Electronics Design -- Chapter 3 Verilog HDL for Digital and Analog Design -- Chapter 4 Introduction to Hardware Description Languages -- Chapter 5 Introduction to Hardware Description Languages (HDLs) -- Chapter 6 Emerging Trends in Nanoscale Semiconductor Devices -- Chapter 7 Design Challenges and Solutions in CMOS-Based FET -- Chapter 8 Analytical Design of FET-Based Biosensors -- Chapter 9 Low-Power FET-Based Biosensors -- Chapter 10 Nanowire Array-Based Gate-All-Around MOSFET for Next-Generation Memory Devices -- Chapter 11 Design of 7T SRAM Cell Using FinFET Technology -- Chapter 12 Performance Analysis of AlGaN/GaN Heterostructure Field-Effect Transistor (HFET) -- Chapter 13 Synthesis of Polymer-Based Composites for Application in Field-Effect Transistors -- Chapter 14 Power Efficiency Analysis of Low-Power Circuit Design Techniques in 90-nm CMOS Technology -- Chapter 15 Macromodeling and Synthesis of Analog Circuits -- Chapter 16 Performance-Linked Phase-Locked Loop Architectures: Recent Developments -- Chapter 17 Review of Analog-to-Digital and Digital-to-Analog Converters for A Smart Antenna Application -- Chapter 18 Active Inductor-Based VCO for Wireless Communication -- Chapter 19 Fault Simulation Algorithms: Verilog Implementation -- Chapter 20 Hardware Protection through Logic Obfuscation -- Index Integrated circuits-Very large scale integration-Design and construction VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4117388-0 |
| title | Advanced VLSI design and testability issues |
| title_auth | Advanced VLSI design and testability issues |
| title_exact_search | Advanced VLSI design and testability issues |
| title_exact_search_txtP | Advanced VLSI design and testability issues |
| title_full | Advanced VLSI design and testability issues edited bySuman Lata Tripathi, Sobhit Saxena, and Sushanta Kumar Mohapatra |
| title_fullStr | Advanced VLSI design and testability issues edited bySuman Lata Tripathi, Sobhit Saxena, and Sushanta Kumar Mohapatra |
| title_full_unstemmed | Advanced VLSI design and testability issues edited bySuman Lata Tripathi, Sobhit Saxena, and Sushanta Kumar Mohapatra |
| title_short | Advanced VLSI design and testability issues |
| title_sort | advanced vlsi design and testability issues |
| topic | Integrated circuits-Very large scale integration-Design and construction VLSI (DE-588)4117388-0 gnd |
| topic_facet | Integrated circuits-Very large scale integration-Design and construction VLSI |
| url | https://doi.org/10.1201/9781003083436 |
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