ASIC Design and Synthesis: RTL Design Using Verilog
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Singapore
Springer Singapore
2021
Singapore Springer [2021] |
| Ausgabe: | 1st ed. 2021 |
| Schlagworte: | |
| Online-Zugang: | DE-634 DE-1043 DE-1046 DE-858 DE-Aug4 DE-1050 DE-573 DE-M347 DE-92 DE-898 DE-859 DE-860 DE-861 DE-863 DE-862 DE-523 DE-91 DE-706 DE-29 URL des Erstveröffentlichers |
| Beschreibung: | 1 Online-Ressource (XXI, 330 p. 311 illus., 184 illus. in color) |
| ISBN: | 9789813346420 |
| DOI: | 10.1007/978-981-33-4642-0 |
Internformat
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Datensatz im Suchindex
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| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik Maschinenbau |
| discipline_str_mv | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik Maschinenbau |
| doi_str_mv | 10.1007/978-981-33-4642-0 |
| edition | 1st ed. 2021 |
| format | Electronic eBook |
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| illustrated | Not Illustrated |
| index_date | 2024-07-03T16:33:50Z |
| indexdate | 2025-02-20T07:01:37Z |
| institution | BVB |
| isbn | 9789813346420 |
| language | English |
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| physical | 1 Online-Ressource (XXI, 330 p. 311 illus., 184 illus. in color) |
| psigel | ZDB-2-ENG ZDB-2-ENG_2021 |
| publishDate | 2021 |
| publishDateSearch | 2021 |
| publishDateSort | 2021 |
| publisher | Springer Singapore Springer |
| record_format | marc |
| spellingShingle | Taraate, Vaibbhav ASIC Design and Synthesis RTL Design Using Verilog Circuits and Systems Control Structures and Microprogramming Logic Design Electronic circuits Microprogramming Logic design |
| title | ASIC Design and Synthesis RTL Design Using Verilog |
| title_auth | ASIC Design and Synthesis RTL Design Using Verilog |
| title_exact_search | ASIC Design and Synthesis RTL Design Using Verilog |
| title_exact_search_txtP | ASIC Design and Synthesis RTL Design Using Verilog |
| title_full | ASIC Design and Synthesis RTL Design Using Verilog by Vaibbhav Taraate |
| title_fullStr | ASIC Design and Synthesis RTL Design Using Verilog by Vaibbhav Taraate |
| title_full_unstemmed | ASIC Design and Synthesis RTL Design Using Verilog by Vaibbhav Taraate |
| title_short | ASIC Design and Synthesis |
| title_sort | asic design and synthesis rtl design using verilog |
| title_sub | RTL Design Using Verilog |
| topic | Circuits and Systems Control Structures and Microprogramming Logic Design Electronic circuits Microprogramming Logic design |
| topic_facet | Circuits and Systems Control Structures and Microprogramming Logic Design Electronic circuits Microprogramming Logic design |
| url | https://doi.org/10.1007/978-981-33-4642-0 |
| work_keys_str_mv | AT taraatevaibbhav asicdesignandsynthesisrtldesignusingverilog |