The e Hardware Verification Language:
I am glad to see this new book on the e language and on verification. I am especially glad to see a description of the e Reuse Methodology (eRM). The main goal of verification is, after all, finding more bugs quicker using given resources, and verification reuse (module-to-system, old-system-to-new-...
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
New York, NY
Springer US
2004
|
| Edition: | 1st ed. 2004 |
| Subjects: | |
| Online Access: | UBY01 Volltext |
| Summary: | I am glad to see this new book on the e language and on verification. I am especially glad to see a description of the e Reuse Methodology (eRM). The main goal of verification is, after all, finding more bugs quicker using given resources, and verification reuse (module-to-system, old-system-to-new-system etc. ) is a key enabling component. This book offers a fresh approach in teaching the e hardware verification language within the context of coverage driven verification methodology. I hope it will help the reader und- stand the many important and interesting topics surrounding hardware verification. Yoav Hollander Founder and CTO, Verisity Inc. Preface This book provides a detailed coverage of the e hardware verification language (HVL), state of the art verification methodologies, and the use of e HVL as a facilitating verification tool in implementing a state of the art verification environment. It includes comprehensive descriptions of the new concepts introduced by the e language, e language syntax, and its as- ciated semantics. This book also describes the architectural views and requirements of verifi- tion environments (randomly generated environments, coverage driven verification environments, etc. ), verification blocks in the architectural views (i. e. generators, initiators, c- lectors, checkers, monitors, coverage definitions, etc. ) and their implementations using the e HVL. Moreover, the e Reuse Methodology (eRM), the motivation for defining such a gui- line, and step-by-step instructions for building an eRM compliant e Verification Component (eVC) are also discussed |
| Physical Description: | 1 Online-Ressource (XXII, 349 p) |
| ISBN: | 9781402080241 |
| DOI: | 10.1007/b117092 |
Staff View
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| 520 | |a I am glad to see this new book on the e language and on verification. I am especially glad to see a description of the e Reuse Methodology (eRM). The main goal of verification is, after all, finding more bugs quicker using given resources, and verification reuse (module-to-system, old-system-to-new-system etc. ) is a key enabling component. This book offers a fresh approach in teaching the e hardware verification language within the context of coverage driven verification methodology. I hope it will help the reader und- stand the many important and interesting topics surrounding hardware verification. Yoav Hollander Founder and CTO, Verisity Inc. Preface This book provides a detailed coverage of the e hardware verification language (HVL), state of the art verification methodologies, and the use of e HVL as a facilitating verification tool in implementing a state of the art verification environment. It includes comprehensive descriptions of the new concepts introduced by the e language, e language syntax, and its as- ciated semantics. This book also describes the architectural views and requirements of verifi- tion environments (randomly generated environments, coverage driven verification environments, etc. ), verification blocks in the architectural views (i. e. generators, initiators, c- lectors, checkers, monitors, coverage definitions, etc. ) and their implementations using the e HVL. Moreover, the e Reuse Methodology (eRM), the motivation for defining such a gui- line, and step-by-step instructions for building an eRM compliant e Verification Component (eVC) are also discussed | ||
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| id | DE-604.BV047064599 |
| illustrated | Not Illustrated |
| index_date | 2024-07-03T16:12:22Z |
| indexdate | 2024-07-10T09:01:35Z |
| institution | BVB |
| isbn | 9781402080241 |
| language | English |
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| physical | 1 Online-Ressource (XXII, 349 p) |
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| publisher | Springer US |
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| spelling | Iman, Sasan Verfasser aut The e Hardware Verification Language by Sasan Iman, Sunita Joshi 1st ed. 2004 New York, NY Springer US 2004 1 Online-Ressource (XXII, 349 p) txt rdacontent c rdamedia cr rdacarrier I am glad to see this new book on the e language and on verification. I am especially glad to see a description of the e Reuse Methodology (eRM). The main goal of verification is, after all, finding more bugs quicker using given resources, and verification reuse (module-to-system, old-system-to-new-system etc. ) is a key enabling component. This book offers a fresh approach in teaching the e hardware verification language within the context of coverage driven verification methodology. I hope it will help the reader und- stand the many important and interesting topics surrounding hardware verification. Yoav Hollander Founder and CTO, Verisity Inc. Preface This book provides a detailed coverage of the e hardware verification language (HVL), state of the art verification methodologies, and the use of e HVL as a facilitating verification tool in implementing a state of the art verification environment. It includes comprehensive descriptions of the new concepts introduced by the e language, e language syntax, and its as- ciated semantics. This book also describes the architectural views and requirements of verifi- tion environments (randomly generated environments, coverage driven verification environments, etc. ), verification blocks in the architectural views (i. e. generators, initiators, c- lectors, checkers, monitors, coverage definitions, etc. ) and their implementations using the e HVL. Moreover, the e Reuse Methodology (eRM), the motivation for defining such a gui- line, and step-by-step instructions for building an eRM compliant e Verification Component (eVC) are also discussed Theory of Computation Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computers Electronic circuits Electrical engineering Computer-aided engineering Joshi, Sunita aut Erscheint auch als Druck-Ausgabe 9781475779264 Erscheint auch als Druck-Ausgabe 9781402080234 Erscheint auch als Druck-Ausgabe 9781475779257 https://doi.org/10.1007/b117092 Verlag URL des Eerstveröffentlichers Volltext |
| spellingShingle | Iman, Sasan Joshi, Sunita The e Hardware Verification Language Theory of Computation Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computers Electronic circuits Electrical engineering Computer-aided engineering |
| title | The e Hardware Verification Language |
| title_auth | The e Hardware Verification Language |
| title_exact_search | The e Hardware Verification Language |
| title_exact_search_txtP | The e Hardware Verification Language |
| title_full | The e Hardware Verification Language by Sasan Iman, Sunita Joshi |
| title_fullStr | The e Hardware Verification Language by Sasan Iman, Sunita Joshi |
| title_full_unstemmed | The e Hardware Verification Language by Sasan Iman, Sunita Joshi |
| title_short | The e Hardware Verification Language |
| title_sort | the e hardware verification language |
| topic | Theory of Computation Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computers Electronic circuits Electrical engineering Computer-aided engineering |
| topic_facet | Theory of Computation Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computers Electronic circuits Electrical engineering Computer-aided engineering |
| url | https://doi.org/10.1007/b117092 |
| work_keys_str_mv | AT imansasan theehardwareverificationlanguage AT joshisunita theehardwareverificationlanguage |