A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures:
Despite five decades of research, parallel computing remains an exotic, frontier technology on the fringes of mainstream computing. Its much-heralded triumph over sequential computing has yet to materialize. This is in spite of the fact that the processing needs of many signal processing application...
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| Hauptverfasser: | , |
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| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
Springer US
2003
|
| Ausgabe: | 1st ed. 2003 |
| Schriftenreihe: | Series in Computer Science
|
| Schlagworte: | |
| Online-Zugang: | UBY01 Volltext |
| Zusammenfassung: | Despite five decades of research, parallel computing remains an exotic, frontier technology on the fringes of mainstream computing. Its much-heralded triumph over sequential computing has yet to materialize. This is in spite of the fact that the processing needs of many signal processing applications continue to eclipse the capabilities of sequential computing. The culprit is largely the software development environment. Fundamental shortcomings in the development environment of many parallel computer architectures thwart the adoption of parallel computing. Foremost, parallel computing has no unifying model to accurately predict the execution time of algorithms on parallel architectures. Cost and scarce programming resources prohibit deploying multiple algorithms and partitioning strategies in an attempt to find the fastest solution. As a consequence, algorithm design is largely an intuitive art form dominated by practitioners who specialize in a particular computer architecture. This, coupled with the fact that parallel computer architectures rarely last more than a couple of years, makes for a complex and challenging design environment. To navigate this environment, algorithm designers need a road map, a detailed procedure they can use to efficiently develop high performance, portable parallel algorithms. The focus of this book is to draw such a road map. The Parallel Algorithm Synthesis Procedure can be used to design reusable building blocks of adaptable, scalable software modules from which high performance signal processing applications can be constructed. The hallmark of the procedure is a semi-systematic process for introducing parameters to control the partitioning and scheduling of computation and communication. This facilitates the tailoring of software modules to exploit different configurations of multiple processors, multiple floating-point units, and hierarchical memories. To showcase the efficacy of this procedure, the book presents three case studies requiring various degrees of optimization for parallel execution |
| Beschreibung: | 1 Online-Ressource (XI, 108 p) |
| ISBN: | 9781441986504 |
| DOI: | 10.1007/978-1-4419-8650-4 |
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| 520 | |a Despite five decades of research, parallel computing remains an exotic, frontier technology on the fringes of mainstream computing. Its much-heralded triumph over sequential computing has yet to materialize. This is in spite of the fact that the processing needs of many signal processing applications continue to eclipse the capabilities of sequential computing. The culprit is largely the software development environment. Fundamental shortcomings in the development environment of many parallel computer architectures thwart the adoption of parallel computing. Foremost, parallel computing has no unifying model to accurately predict the execution time of algorithms on parallel architectures. Cost and scarce programming resources prohibit deploying multiple algorithms and partitioning strategies in an attempt to find the fastest solution. As a consequence, algorithm design is largely an intuitive art form dominated by practitioners who specialize in a particular computer architecture. | ||
| 520 | |a This, coupled with the fact that parallel computer architectures rarely last more than a couple of years, makes for a complex and challenging design environment. To navigate this environment, algorithm designers need a road map, a detailed procedure they can use to efficiently develop high performance, portable parallel algorithms. The focus of this book is to draw such a road map. The Parallel Algorithm Synthesis Procedure can be used to design reusable building blocks of adaptable, scalable software modules from which high performance signal processing applications can be constructed. The hallmark of the procedure is a semi-systematic process for introducing parameters to control the partitioning and scheduling of computation and communication. This facilitates the tailoring of software modules to exploit different configurations of multiple processors, multiple floating-point units, and hierarchical memories. | ||
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| edition | 1st ed. 2003 |
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| index_date | 2024-07-03T16:12:21Z |
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| isbn | 9781441986504 |
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| spelling | Dunn, Ian N. Verfasser aut A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures by Ian N. Dunn, Gerard G.L. Meyer 1st ed. 2003 New York, NY Springer US 2003 1 Online-Ressource (XI, 108 p) txt rdacontent c rdamedia cr rdacarrier Series in Computer Science Despite five decades of research, parallel computing remains an exotic, frontier technology on the fringes of mainstream computing. Its much-heralded triumph over sequential computing has yet to materialize. This is in spite of the fact that the processing needs of many signal processing applications continue to eclipse the capabilities of sequential computing. The culprit is largely the software development environment. Fundamental shortcomings in the development environment of many parallel computer architectures thwart the adoption of parallel computing. Foremost, parallel computing has no unifying model to accurately predict the execution time of algorithms on parallel architectures. Cost and scarce programming resources prohibit deploying multiple algorithms and partitioning strategies in an attempt to find the fastest solution. As a consequence, algorithm design is largely an intuitive art form dominated by practitioners who specialize in a particular computer architecture. This, coupled with the fact that parallel computer architectures rarely last more than a couple of years, makes for a complex and challenging design environment. To navigate this environment, algorithm designers need a road map, a detailed procedure they can use to efficiently develop high performance, portable parallel algorithms. The focus of this book is to draw such a road map. The Parallel Algorithm Synthesis Procedure can be used to design reusable building blocks of adaptable, scalable software modules from which high performance signal processing applications can be constructed. The hallmark of the procedure is a semi-systematic process for introducing parameters to control the partitioning and scheduling of computation and communication. This facilitates the tailoring of software modules to exploit different configurations of multiple processors, multiple floating-point units, and hierarchical memories. To showcase the efficacy of this procedure, the book presents three case studies requiring various degrees of optimization for parallel execution Theory of Computation Processor Architectures Linear and Multilinear Algebras, Matrix Theory Algorithms Signal, Image and Speech Processing Computers Microprocessors Matrix theory Algebra Signal processing Image processing Speech processing systems Paralleler Algorithmus (DE-588)4193615-2 gnd rswk-swf Hochleistungsrechnen (DE-588)4532701-4 gnd rswk-swf Hochleistungsrechnen (DE-588)4532701-4 s Paralleler Algorithmus (DE-588)4193615-2 s DE-604 Meyer, Gerard G.L. aut Erscheint auch als Druck-Ausgabe 9781461346586 Erscheint auch als Druck-Ausgabe 9780306477430 Erscheint auch als Druck-Ausgabe 9781441986511 https://doi.org/10.1007/978-1-4419-8650-4 Verlag URL des Eerstveröffentlichers Volltext |
| spellingShingle | Dunn, Ian N. Meyer, Gerard G.L A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures Theory of Computation Processor Architectures Linear and Multilinear Algebras, Matrix Theory Algorithms Signal, Image and Speech Processing Computers Microprocessors Matrix theory Algebra Signal processing Image processing Speech processing systems Paralleler Algorithmus (DE-588)4193615-2 gnd Hochleistungsrechnen (DE-588)4532701-4 gnd |
| subject_GND | (DE-588)4193615-2 (DE-588)4532701-4 |
| title | A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures |
| title_auth | A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures |
| title_exact_search | A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures |
| title_exact_search_txtP | A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures |
| title_full | A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures by Ian N. Dunn, Gerard G.L. Meyer |
| title_fullStr | A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures by Ian N. Dunn, Gerard G.L. Meyer |
| title_full_unstemmed | A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures by Ian N. Dunn, Gerard G.L. Meyer |
| title_short | A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures |
| title_sort | a parallel algorithm synthesis procedure for high performance computer architectures |
| topic | Theory of Computation Processor Architectures Linear and Multilinear Algebras, Matrix Theory Algorithms Signal, Image and Speech Processing Computers Microprocessors Matrix theory Algebra Signal processing Image processing Speech processing systems Paralleler Algorithmus (DE-588)4193615-2 gnd Hochleistungsrechnen (DE-588)4532701-4 gnd |
| topic_facet | Theory of Computation Processor Architectures Linear and Multilinear Algebras, Matrix Theory Algorithms Signal, Image and Speech Processing Computers Microprocessors Matrix theory Algebra Signal processing Image processing Speech processing systems Paralleler Algorithmus Hochleistungsrechnen |
| url | https://doi.org/10.1007/978-1-4419-8650-4 |
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