Computer organization and design: the hardware/software interface
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam ; Boston ; Heidelberg ; London ; New York ; Oxford ; Paris ; San Diego ; San Francisco ; Singapore ; Sydney ; Tokyo
Morgan Kaufmann
[2021]
|
| Ausgabe: | Sixth edition, MIPS edition |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | 1 Band (verschiedene Seitenzählungen) Diagramme |
| ISBN: | 9780128201091 0128237163 9780128237168 0128201096 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV047031319 | ||
| 003 | DE-604 | ||
| 005 | 20240305 | ||
| 007 | t | ||
| 008 | 201126s2021 |||| |||| 00||| eng d | ||
| 020 | |a 9780128201091 |9 978-0-12-820109-1 | ||
| 020 | |a 0128237163 |9 0-12-823716-3 | ||
| 020 | |a 9780128237168 |9 978-0-12-823716-8 | ||
| 020 | |a 0128201096 |9 0-12-820109-6 | ||
| 035 | |a (OCoLC)1235886860 | ||
| 035 | |a (DE-599)BVBBV047031319 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91G |a DE-92 |a DE-573 |a DE-29T |a DE-739 |a DE-703 |a DE-898 |a DE-20 |a DE-188 | ||
| 084 | |a ST 150 |0 (DE-625)143594: |2 rvk | ||
| 084 | |a ST 110 |0 (DE-625)143583: |2 rvk | ||
| 084 | |a DAT 200 |2 stub | ||
| 100 | 1 | |a Patterson, David A. |d 1947- |e Verfasser |0 (DE-588)114326452 |4 aut | |
| 245 | 1 | 0 | |a Computer organization and design |b the hardware/software interface |c David A. Patterson (University of California, Berkeley, Google, Inc.), John L. Hennessy (Stanford University) |
| 250 | |a Sixth edition, MIPS edition | ||
| 264 | 1 | |a Amsterdam ; Boston ; Heidelberg ; London ; New York ; Oxford ; Paris ; San Diego ; San Francisco ; Singapore ; Sydney ; Tokyo |b Morgan Kaufmann |c [2021] | |
| 300 | |a 1 Band (verschiedene Seitenzählungen) |b Diagramme | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a Computerarchitektur |0 (DE-588)4048717-9 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Softwareschnittstelle |0 (DE-588)4116525-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Benutzeroberfläche |0 (DE-588)4131424-4 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Computerarchitektur |0 (DE-588)4048717-9 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Softwareschnittstelle |0 (DE-588)4116525-1 |D s |
| 689 | 1 | |5 DE-604 | |
| 689 | 2 | 0 | |a Benutzeroberfläche |0 (DE-588)4131424-4 |D s |
| 689 | 2 | |5 DE-604 | |
| 700 | 1 | |a Hennessy, John L. |d 1952- |e Verfasser |0 (DE-588)114326436 |4 aut | |
| 776 | 0 | 8 | |i Erscheint auch als |n Online-Ausgabe |z 978-0-12-822674-2 |
| 856 | 4 | 2 | |m Digitalisierung UB Passau - ADAM Catalogue Enrichment |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=032438579&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-032438579 | ||
Datensatz im Suchindex
| _version_ | 1804182003987251200 |
|---|---|
| adam_text | Contents Preface xv CHAPTERS Computer Abstractions and Technology 2 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 1.15 Introduction 3 Seven Great Ideas in Computer Architecture 10 Below Your Program 13 Under the Covers 16 Technologies for Building Processors and Memory 24 Performance 28 The Power Wall 40 The Sea Change: The Switch from Uniprocessors to Multiprocessors Real Stuff: Benchmarking the Intel Core І7 46 Going Faster: Matrix Multiply in Python 49 Fallacies and Pitfalls 50 Concluding Remarks 53 Historical Perspective and Further Reading 55 Self-Study 55 Exercises 59 Instructions: Language of the Computer 66 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 Introduction 68 Operations of the Computer Hardware 69 Operands of the Computer Hardware 72 Signed and Unsigned Numbers 79 Representing Instructions in the Computer 86 Logical Operations 93 Instructions for Making Decisions 96 Supporting Procedures in Computer Hardware 102 Communicating with People 112 MIPS Addressing for 32-Bit Immediates and Addresses Parallelism and Instructions: Synchronization 127 Translating and Starting a Program 129 A C Sort Example to Put It All Together 138 118
x Contents 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 2.23 2.24 2.25 Arrays versus Pointers 147 Advanced Material: Compiling C and Interpreting Java Real Stuff: ARMv7 (32-bit) Instructions 151 Real Stuff: ARMv8 (64-bit) Instructions 155 Real Stuff: RISC-V Instructions 156 Real Stuff: x86 Instructions 157 Going Faster: Matrix Multiply in C 166 Fallacies and Pitfalls 167 Concluding Remarks 169 Historical Perspective and Further Reading 172 Self Study 172 Exercises 175 Arithmetic for Computers 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 186 Introduction 188 Addition and Subtraction 188 Multiplication 193 Division 199 Floating Point 206 Parallelism and Computer Arithmetic: Subword Parallelism 232 Real Stuff: Streaming SIMD Extensions and Advanced Vector Exten sions in x86 234 Going Faster: Subword Parallelism and Matrix Multiply 235 Fallacies and Pitfalls 237 Concluding Remarks 241 Historical Perspective and Further Reading 245 Self Study 245 Exercises 248 The Processor 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 151 254 Introduction 256 Logic Design Conventions 260 Building a Datapath 263 A Simple Implementation Scheme 271 A Multicycle Implementation 284 An Overview of Pipelining 285 Pipelined Datapath and Control 298 Data Hazards: Forwarding versus Stalling 315 Control Hazards 328 Exceptions 337 Parallelism via Instructions 344 Putting It All Together: The Intel Core i7 6700 and ARM Cortex-A53 358
Contents 4.13 Going Faster: Instruction-Level Parallelism and Matrix Multiply 366 4.14 Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations 368 4.15 Fallacies and Pitfalls 369 4.16 Concluding Remarks 370 4.17 Historical Perspective and Further Reading 371 4.18 Self-Study 371 4.19 Exercises 372 Large and Fast: Exploiting Memory Hierarchy 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 Introduction 392 Memory Technologies 396 The Basics of Caches 401 Measuring and Improving Cache Performance 416 Dependable Memory Hierarchy 436 Virtual Machines 442 Virtual Memory 446 A Common Framework for Memory Hierarchy 472 Using a Finite-State Machine to Control a Simple Cache 479 Parallelism and Memory Hierarchies: Cache Coherence 484 Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks 488 Advanced Material: Implementing Cache Controllers 488 Real Stuif: The ARM Cortex-A8 and Intel Core i7 Memory Hierarchies 489 Going Faster: Cache Blocking and Matrix Multiply 494 Fallacies and Pitfalls 496 Concluding Remarks 500 Historical Perspective and Further Reading 501 Self-Study 501 Exercises 506 Parallel Processors from Client to Cloud 6.1 6.2 6.3 6.4 6.5 6.6 6.7 390 524 Introduction 526 The Difficulty of Creating Parallel Processing Programs 528 SISD, MIMD, SIMD, SPMD, and Vector 533 Hardware Multithreading 540 Multicore and Other Shared Memory Multiprocessors 543 Introduction to Graphics Processing Units 548 Domain Specific Architectures 555
xi
xii Contents 6.8 Ü Щ 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 Clusters, Warehouse Scale Computers, and Other MessagePassing Multiprocessors 558 Introduction to Multiprocessor Network Topologies 563 Communicating to the Outside World: Cluster Networking 566 Multiprocessor Benchmarks and Performance Models 567 Real Stuff: Benchmarking the Google TPUv3 Supercomputer and an NVIDIA Volta GPU Cluster 577 Going Faster: Multiple Processors and Matrix Multiply 586 Fallacies and Pitfalls 589 Concluding Remarks 592 Historical Perspective and Further Reading 594 Self Study 594 Exercises 596 APPENDICES Assemblers, Linkers, and the SPIM Simulator A-610 A.l A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A. 10 A. 11 A. 12 Introduction A-611 Assemblers A-618 Linkers A-626 Loading A-627 Memory Usage A-628 Procedure Call Convention A-630 Exceptions and Interrupts A-641 Input and Output A-646 SPIM A-648 MIPS R2000 Assembly Language A-653 Concluding Remarks A-689 Exercises A-690 The Basics of Logic Design B. l B.2 B.3 B.4 B.5 B.6 B.7 B.8 B.9 B.10 B-692 Introduction B-693 Gates, Truth Tables, and Logic Equations B-694 Combinational Logic B-699 Using a Hardware Description Language B-710 Constructing a Basic Arithmetic Logic Unit B-716 Faster Addition: Carry Lookahead B-728 Clocks B-738 Memory Elements: Flip-Flops, Latches, and Registers Memory Elements: SRAMs and DRAMs B-748 Finite-State Machines B-757 B-740
Contents Index B.ll B.12 B.13 B.14 1-І ONLINE Timing Methodologies B-762 Field Programmable Devices B-768 Concluding Remarks B-769 Exercises B-770 CONTENT Graphics and Computing GPUs C-2 C.l C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.l 1 Introduction C-3 GPU System Architectures C-7 Programming GPUs C-12 Multithreaded Multiprocessor Architecture C-25 Parallel Memory System C-36 Floating Point Arithmetic C-41 Real Stuff: The NVIDIA GeForce 8800 C-46 Real Stuff: Mapping Applications to GPUs C-55 Fallacies and Pitfalls C-72 Concluding Remarks C-76 Historical Perspective and Further Reading C-77 Mapping Control to Hardware D-2 D.l Introduction D-3 D.2 Implementing Combinational Control Units D-4 D.3 Implementing Finite-State Machine Control D-8 D.4 Implementing the Next-State Function with a Sequencer D.5 Translating a Microprogram to Hardware D-28 D.6 Concluding Remarks D-32 D.7 Exercises D-33 D-22 Survey of Instruction Set Architectures E.I E.2 E.3 E.4 E.5 E.6 Introduction E-3 A Survey of RISC Architecture for Desktop, Server, and Embedded Computers E-4 The Intel 80x86 E-30 The VAX Architecture E-50 The IBM 360/370 Architecture for Mainframe Computers E-69 Historical Perspective and References E-73 § Glossary G-l § Further Reading FR-1 xiii
|
| adam_txt |
Contents Preface xv CHAPTERS Computer Abstractions and Technology 2 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 1.15 Introduction 3 Seven Great Ideas in Computer Architecture 10 Below Your Program 13 Under the Covers 16 Technologies for Building Processors and Memory 24 Performance 28 The Power Wall 40 The Sea Change: The Switch from Uniprocessors to Multiprocessors Real Stuff: Benchmarking the Intel Core І7 46 Going Faster: Matrix Multiply in Python 49 Fallacies and Pitfalls 50 Concluding Remarks 53 Historical Perspective and Further Reading 55 Self-Study 55 Exercises 59 Instructions: Language of the Computer 66 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 Introduction 68 Operations of the Computer Hardware 69 Operands of the Computer Hardware 72 Signed and Unsigned Numbers 79 Representing Instructions in the Computer 86 Logical Operations 93 Instructions for Making Decisions 96 Supporting Procedures in Computer Hardware 102 Communicating with People 112 MIPS Addressing for 32-Bit Immediates and Addresses Parallelism and Instructions: Synchronization 127 Translating and Starting a Program 129 A C Sort Example to Put It All Together 138 118
x Contents 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 2.23 2.24 2.25 Arrays versus Pointers 147 Advanced Material: Compiling C and Interpreting Java Real Stuff: ARMv7 (32-bit) Instructions 151 Real Stuff: ARMv8 (64-bit) Instructions 155 Real Stuff: RISC-V Instructions 156 Real Stuff: x86 Instructions 157 Going Faster: Matrix Multiply in C 166 Fallacies and Pitfalls 167 Concluding Remarks 169 Historical Perspective and Further Reading 172 Self Study 172 Exercises 175 Arithmetic for Computers 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 186 Introduction 188 Addition and Subtraction 188 Multiplication 193 Division 199 Floating Point 206 Parallelism and Computer Arithmetic: Subword Parallelism 232 Real Stuff: Streaming SIMD Extensions and Advanced Vector Exten sions in x86 234 Going Faster: Subword Parallelism and Matrix Multiply 235 Fallacies and Pitfalls 237 Concluding Remarks 241 Historical Perspective and Further Reading 245 Self Study 245 Exercises 248 The Processor 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 151 254 Introduction 256 Logic Design Conventions 260 Building a Datapath 263 A Simple Implementation Scheme 271 A Multicycle Implementation 284 An Overview of Pipelining 285 Pipelined Datapath and Control 298 Data Hazards: Forwarding versus Stalling 315 Control Hazards 328 Exceptions 337 Parallelism via Instructions 344 Putting It All Together: The Intel Core i7 6700 and ARM Cortex-A53 358
Contents 4.13 Going Faster: Instruction-Level Parallelism and Matrix Multiply 366 4.14 Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations 368 4.15 Fallacies and Pitfalls 369 4.16 Concluding Remarks 370 4.17 Historical Perspective and Further Reading 371 4.18 Self-Study 371 4.19 Exercises 372 Large and Fast: Exploiting Memory Hierarchy 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 Introduction 392 Memory Technologies 396 The Basics of Caches 401 Measuring and Improving Cache Performance 416 Dependable Memory Hierarchy 436 Virtual Machines 442 Virtual Memory 446 A Common Framework for Memory Hierarchy 472 Using a Finite-State Machine to Control a Simple Cache 479 Parallelism and Memory Hierarchies: Cache Coherence 484 Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks 488 Advanced Material: Implementing Cache Controllers 488 Real Stuif: The ARM Cortex-A8 and Intel Core i7 Memory Hierarchies 489 Going Faster: Cache Blocking and Matrix Multiply 494 Fallacies and Pitfalls 496 Concluding Remarks 500 Historical Perspective and Further Reading 501 Self-Study 501 Exercises 506 Parallel Processors from Client to Cloud 6.1 6.2 6.3 6.4 6.5 6.6 6.7 390 524 Introduction 526 The Difficulty of Creating Parallel Processing Programs 528 SISD, MIMD, SIMD, SPMD, and Vector 533 Hardware Multithreading 540 Multicore and Other Shared Memory Multiprocessors 543 Introduction to Graphics Processing Units 548 Domain Specific Architectures 555
xi
xii Contents 6.8 Ü Щ 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 Clusters, Warehouse Scale Computers, and Other MessagePassing Multiprocessors 558 Introduction to Multiprocessor Network Topologies 563 Communicating to the Outside World: Cluster Networking 566 Multiprocessor Benchmarks and Performance Models 567 Real Stuff: Benchmarking the Google TPUv3 Supercomputer and an NVIDIA Volta GPU Cluster 577 Going Faster: Multiple Processors and Matrix Multiply 586 Fallacies and Pitfalls 589 Concluding Remarks 592 Historical Perspective and Further Reading 594 Self Study 594 Exercises 596 APPENDICES Assemblers, Linkers, and the SPIM Simulator A-610 A.l A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A. 10 A. 11 A. 12 Introduction A-611 Assemblers A-618 Linkers A-626 Loading A-627 Memory Usage A-628 Procedure Call Convention A-630 Exceptions and Interrupts A-641 Input and Output A-646 SPIM A-648 MIPS R2000 Assembly Language A-653 Concluding Remarks A-689 Exercises A-690 The Basics of Logic Design B. l B.2 B.3 B.4 B.5 B.6 B.7 B.8 B.9 B.10 B-692 Introduction B-693 Gates, Truth Tables, and Logic Equations B-694 Combinational Logic B-699 Using a Hardware Description Language B-710 Constructing a Basic Arithmetic Logic Unit B-716 Faster Addition: Carry Lookahead B-728 Clocks B-738 Memory Elements: Flip-Flops, Latches, and Registers Memory Elements: SRAMs and DRAMs B-748 Finite-State Machines B-757 B-740
Contents Index B.ll B.12 B.13 B.14 1-І ONLINE Timing Methodologies B-762 Field Programmable Devices B-768 Concluding Remarks B-769 Exercises B-770 CONTENT Graphics and Computing GPUs C-2 C.l C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.l 1 Introduction C-3 GPU System Architectures C-7 Programming GPUs C-12 Multithreaded Multiprocessor Architecture C-25 Parallel Memory System C-36 Floating Point Arithmetic C-41 Real Stuff: The NVIDIA GeForce 8800 C-46 Real Stuff: Mapping Applications to GPUs C-55 Fallacies and Pitfalls C-72 Concluding Remarks C-76 Historical Perspective and Further Reading C-77 Mapping Control to Hardware D-2 D.l Introduction D-3 D.2 Implementing Combinational Control Units D-4 D.3 Implementing Finite-State Machine Control D-8 D.4 Implementing the Next-State Function with a Sequencer D.5 Translating a Microprogram to Hardware D-28 D.6 Concluding Remarks D-32 D.7 Exercises D-33 D-22 Survey of Instruction Set Architectures E.I E.2 E.3 E.4 E.5 E.6 Introduction E-3 A Survey of RISC Architecture for Desktop, Server, and Embedded Computers E-4 The Intel 80x86 E-30 The VAX Architecture E-50 The IBM 360/370 Architecture for Mainframe Computers E-69 Historical Perspective and References E-73 § Glossary G-l § Further Reading FR-1 xiii |
| any_adam_object | 1 |
| any_adam_object_boolean | 1 |
| author | Patterson, David A. 1947- Hennessy, John L. 1952- |
| author_GND | (DE-588)114326452 (DE-588)114326436 |
| author_facet | Patterson, David A. 1947- Hennessy, John L. 1952- |
| author_role | aut aut |
| author_sort | Patterson, David A. 1947- |
| author_variant | d a p da dap j l h jl jlh |
| building | Verbundindex |
| bvnumber | BV047031319 |
| classification_rvk | ST 150 ST 110 |
| classification_tum | DAT 200 |
| ctrlnum | (OCoLC)1235886860 (DE-599)BVBBV047031319 |
| discipline | Informatik |
| discipline_str_mv | Informatik |
| edition | Sixth edition, MIPS edition |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02253nam a2200481 c 4500</leader><controlfield tag="001">BV047031319</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20240305 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">201126s2021 |||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780128201091</subfield><subfield code="9">978-0-12-820109-1</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0128237163</subfield><subfield code="9">0-12-823716-3</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780128237168</subfield><subfield code="9">978-0-12-823716-8</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0128201096</subfield><subfield code="9">0-12-820109-6</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1235886860</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV047031319</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield><subfield code="a">DE-92</subfield><subfield code="a">DE-573</subfield><subfield code="a">DE-29T</subfield><subfield code="a">DE-739</subfield><subfield code="a">DE-703</subfield><subfield code="a">DE-898</subfield><subfield code="a">DE-20</subfield><subfield code="a">DE-188</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 150</subfield><subfield code="0">(DE-625)143594:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 110</subfield><subfield code="0">(DE-625)143583:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 200</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Patterson, David A.</subfield><subfield code="d">1947-</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)114326452</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Computer organization and design</subfield><subfield code="b">the hardware/software interface</subfield><subfield code="c">David A. Patterson (University of California, Berkeley, Google, Inc.), John L. Hennessy (Stanford University)</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">Sixth edition, MIPS edition</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Amsterdam ; Boston ; Heidelberg ; London ; New York ; Oxford ; Paris ; San Diego ; San Francisco ; Singapore ; Sydney ; Tokyo</subfield><subfield code="b">Morgan Kaufmann</subfield><subfield code="c">[2021]</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Band (verschiedene Seitenzählungen)</subfield><subfield code="b">Diagramme</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Computerarchitektur</subfield><subfield code="0">(DE-588)4048717-9</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Softwareschnittstelle</subfield><subfield code="0">(DE-588)4116525-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Benutzeroberfläche</subfield><subfield code="0">(DE-588)4131424-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Computerarchitektur</subfield><subfield code="0">(DE-588)4048717-9</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Softwareschnittstelle</subfield><subfield code="0">(DE-588)4116525-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Benutzeroberfläche</subfield><subfield code="0">(DE-588)4131424-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Hennessy, John L.</subfield><subfield code="d">1952-</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)114326436</subfield><subfield code="4">aut</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Online-Ausgabe</subfield><subfield code="z">978-0-12-822674-2</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Digitalisierung UB Passau - ADAM Catalogue Enrichment</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=032438579&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-032438579</subfield></datafield></record></collection> |
| id | DE-604.BV047031319 |
| illustrated | Not Illustrated |
| index_date | 2024-07-03T16:02:21Z |
| indexdate | 2024-07-10T09:00:39Z |
| institution | BVB |
| isbn | 9780128201091 0128237163 9780128237168 0128201096 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-032438579 |
| oclc_num | 1235886860 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM DE-92 DE-573 DE-29T DE-739 DE-703 DE-898 DE-BY-UBR DE-20 DE-188 |
| owner_facet | DE-91G DE-BY-TUM DE-92 DE-573 DE-29T DE-739 DE-703 DE-898 DE-BY-UBR DE-20 DE-188 |
| physical | 1 Band (verschiedene Seitenzählungen) Diagramme |
| publishDate | 2021 |
| publishDateSearch | 2021 |
| publishDateSort | 2021 |
| publisher | Morgan Kaufmann |
| record_format | marc |
| spelling | Patterson, David A. 1947- Verfasser (DE-588)114326452 aut Computer organization and design the hardware/software interface David A. Patterson (University of California, Berkeley, Google, Inc.), John L. Hennessy (Stanford University) Sixth edition, MIPS edition Amsterdam ; Boston ; Heidelberg ; London ; New York ; Oxford ; Paris ; San Diego ; San Francisco ; Singapore ; Sydney ; Tokyo Morgan Kaufmann [2021] 1 Band (verschiedene Seitenzählungen) Diagramme txt rdacontent n rdamedia nc rdacarrier Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Softwareschnittstelle (DE-588)4116525-1 gnd rswk-swf Benutzeroberfläche (DE-588)4131424-4 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 s DE-604 Softwareschnittstelle (DE-588)4116525-1 s Benutzeroberfläche (DE-588)4131424-4 s Hennessy, John L. 1952- Verfasser (DE-588)114326436 aut Erscheint auch als Online-Ausgabe 978-0-12-822674-2 Digitalisierung UB Passau - ADAM Catalogue Enrichment application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=032438579&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Patterson, David A. 1947- Hennessy, John L. 1952- Computer organization and design the hardware/software interface Computerarchitektur (DE-588)4048717-9 gnd Softwareschnittstelle (DE-588)4116525-1 gnd Benutzeroberfläche (DE-588)4131424-4 gnd |
| subject_GND | (DE-588)4048717-9 (DE-588)4116525-1 (DE-588)4131424-4 |
| title | Computer organization and design the hardware/software interface |
| title_auth | Computer organization and design the hardware/software interface |
| title_exact_search | Computer organization and design the hardware/software interface |
| title_exact_search_txtP | Computer organization and design the hardware/software interface |
| title_full | Computer organization and design the hardware/software interface David A. Patterson (University of California, Berkeley, Google, Inc.), John L. Hennessy (Stanford University) |
| title_fullStr | Computer organization and design the hardware/software interface David A. Patterson (University of California, Berkeley, Google, Inc.), John L. Hennessy (Stanford University) |
| title_full_unstemmed | Computer organization and design the hardware/software interface David A. Patterson (University of California, Berkeley, Google, Inc.), John L. Hennessy (Stanford University) |
| title_short | Computer organization and design |
| title_sort | computer organization and design the hardware software interface |
| title_sub | the hardware/software interface |
| topic | Computerarchitektur (DE-588)4048717-9 gnd Softwareschnittstelle (DE-588)4116525-1 gnd Benutzeroberfläche (DE-588)4131424-4 gnd |
| topic_facet | Computerarchitektur Softwareschnittstelle Benutzeroberfläche |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=032438579&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT pattersondavida computerorganizationanddesignthehardwaresoftwareinterface AT hennessyjohnl computerorganizationanddesignthehardwaresoftwareinterface |