Resource efficient LDPC decoders: from algorithms to hardware architectures
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
London ; San Diego ; Cambridge ; Oxford
Academic Press, an imprint of Elsevier
[2018]
|
| Schlagworte: | |
| Beschreibung: | Includes bibliographical references and index |
| Beschreibung: | xv, 174 Seiten Illustrationen, Diagramme 24 cm |
| ISBN: | 9780128112557 0128112557 |
Internformat
MARC
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| 100 | 1 | |a Chandrasetty, Vikram Arkalgud |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Resource efficient LDPC decoders |b from algorithms to hardware architectures |c Vikram Arkalgud Chandrasetty, Principal Engineer - ASIC Design Engineering, Western Digital Corporation, Bengaluru, India; Syed Mahfuzul Aziz, Professor - Electrical and Electronic Engineering, University of South Australia, Adelaide, South Australia, Australia |
| 264 | 1 | |a London ; San Diego ; Cambridge ; Oxford |b Academic Press, an imprint of Elsevier |c [2018] | |
| 300 | |a xv, 174 Seiten |b Illustrationen, Diagramme |c 24 cm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Includes bibliographical references and index | ||
| 650 | 4 | |a Decoders (Electronics) / fast / (OCoLC)fst00889111 | |
| 650 | 4 | |a Digital communications / fast / (OCoLC)fst00893634 | |
| 650 | 4 | |a Decoders (Electronics) | |
| 650 | 4 | |a Digital communications | |
| 700 | 1 | |a Aziz, Syed Mahfuzul |e Verfasser |0 (DE-588)1220245003 |4 aut | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-032299790 | ||
Datensatz im Suchindex
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| author | Chandrasetty, Vikram Arkalgud Aziz, Syed Mahfuzul |
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV046889946 |
| illustrated | Illustrated |
| index_date | 2024-07-03T15:20:49Z |
| indexdate | 2024-07-10T08:56:41Z |
| institution | BVB |
| isbn | 9780128112557 0128112557 |
| language | English |
| lccn | 017962394 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-032299790 |
| oclc_num | 1027472730 |
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| owner | DE-19 DE-BY-UBM |
| owner_facet | DE-19 DE-BY-UBM |
| physical | xv, 174 Seiten Illustrationen, Diagramme 24 cm |
| publishDate | 2018 |
| publishDateSearch | 2018 |
| publishDateSort | 2018 |
| publisher | Academic Press, an imprint of Elsevier |
| record_format | marc |
| spelling | Chandrasetty, Vikram Arkalgud Verfasser aut Resource efficient LDPC decoders from algorithms to hardware architectures Vikram Arkalgud Chandrasetty, Principal Engineer - ASIC Design Engineering, Western Digital Corporation, Bengaluru, India; Syed Mahfuzul Aziz, Professor - Electrical and Electronic Engineering, University of South Australia, Adelaide, South Australia, Australia London ; San Diego ; Cambridge ; Oxford Academic Press, an imprint of Elsevier [2018] xv, 174 Seiten Illustrationen, Diagramme 24 cm txt rdacontent n rdamedia nc rdacarrier Includes bibliographical references and index Decoders (Electronics) / fast / (OCoLC)fst00889111 Digital communications / fast / (OCoLC)fst00893634 Decoders (Electronics) Digital communications Aziz, Syed Mahfuzul Verfasser (DE-588)1220245003 aut |
| spellingShingle | Chandrasetty, Vikram Arkalgud Aziz, Syed Mahfuzul Resource efficient LDPC decoders from algorithms to hardware architectures Decoders (Electronics) / fast / (OCoLC)fst00889111 Digital communications / fast / (OCoLC)fst00893634 Decoders (Electronics) Digital communications |
| title | Resource efficient LDPC decoders from algorithms to hardware architectures |
| title_auth | Resource efficient LDPC decoders from algorithms to hardware architectures |
| title_exact_search | Resource efficient LDPC decoders from algorithms to hardware architectures |
| title_exact_search_txtP | Resource efficient LDPC decoders from algorithms to hardware architectures |
| title_full | Resource efficient LDPC decoders from algorithms to hardware architectures Vikram Arkalgud Chandrasetty, Principal Engineer - ASIC Design Engineering, Western Digital Corporation, Bengaluru, India; Syed Mahfuzul Aziz, Professor - Electrical and Electronic Engineering, University of South Australia, Adelaide, South Australia, Australia |
| title_fullStr | Resource efficient LDPC decoders from algorithms to hardware architectures Vikram Arkalgud Chandrasetty, Principal Engineer - ASIC Design Engineering, Western Digital Corporation, Bengaluru, India; Syed Mahfuzul Aziz, Professor - Electrical and Electronic Engineering, University of South Australia, Adelaide, South Australia, Australia |
| title_full_unstemmed | Resource efficient LDPC decoders from algorithms to hardware architectures Vikram Arkalgud Chandrasetty, Principal Engineer - ASIC Design Engineering, Western Digital Corporation, Bengaluru, India; Syed Mahfuzul Aziz, Professor - Electrical and Electronic Engineering, University of South Australia, Adelaide, South Australia, Australia |
| title_short | Resource efficient LDPC decoders |
| title_sort | resource efficient ldpc decoders from algorithms to hardware architectures |
| title_sub | from algorithms to hardware architectures |
| topic | Decoders (Electronics) / fast / (OCoLC)fst00889111 Digital communications / fast / (OCoLC)fst00893634 Decoders (Electronics) Digital communications |
| topic_facet | Decoders (Electronics) / fast / (OCoLC)fst00889111 Digital communications / fast / (OCoLC)fst00893634 Decoders (Electronics) Digital communications |
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