APA-Zitierstil (7. Ausg.)

Taraate, V. (2020). SystemVerilog for Hardware Description: RTL Design and Verification (1st ed. 2020.). Springer Singapore. https://doi.org/10.1007/978-981-15-4405-7

Chicago-Zitierstil (17. Ausg.)

Taraate, Vaibbhav. SystemVerilog for Hardware Description: RTL Design and Verification. 1st ed. 2020. Singapore: Springer Singapore, 2020. https://doi.org/10.1007/978-981-15-4405-7.

MLA-Zitierstil (9. Ausg.)

Taraate, Vaibbhav. SystemVerilog for Hardware Description: RTL Design and Verification. 1st ed. 2020. Springer Singapore, 2020. https://doi.org/10.1007/978-981-15-4405-7.