Baroud, Y. (2019). Memory efficient hardware architectures for data compression and reduction in the parallel image processing domain.
Chicago-Zitierstil (17. Ausg.)Baroud, Yousef. Memory Efficient Hardware Architectures for Data Compression and Reduction in the Parallel Image Processing Domain. Stuttgart, 2019.
MLA-Zitierstil (9. Ausg.)Baroud, Yousef. Memory Efficient Hardware Architectures for Data Compression and Reduction in the Parallel Image Processing Domain. 2019.
Achtung: Diese Zitate sind unter Umständen nicht zu 100% korrekt.