Memory efficient hardware architectures for data compression and reduction in the parallel image processing domain:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Buch |
| Sprache: | English German |
| Veröffentlicht: |
Stuttgart
2019
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis Inhaltsverzeichnis |
| Beschreibung: | 141 Seiten Illustrationen, Diagramme 21 cm |
Internformat
MARC
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| 245 | 1 | 0 | |a Memory efficient hardware architectures for data compression and reduction in the parallel image processing domain |c vorgelegt von Yousef Baroud |
| 264 | 1 | |a Stuttgart |c 2019 | |
| 300 | |a 141 Seiten |b Illustrationen, Diagramme |c 21 cm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 502 | |b Dissertation |c Universität Stuttgart |d 2019 | ||
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Datensatz im Suchindex
| _version_ | 1804181388468944896 |
|---|---|
| adam_text | C
ONTENTS
LIST
OF
FIGURES
11
LIST
OF
TABLES
15
LIST
OF
ABBREVIATIONS
17
1
INTRODUCTION
19
1.1
REGION-BASED
PARALLEL
ENCODING/DECODING
.........................................................
21
1.2
REGION-BASED
IMAGE
FILTERING
................................................................................
24
1.3
CONTRIBUTIONS
.........................................................................................................
26
2
MARKER-FREE
PARALLEL
DECODING
29
2.1
BACKGROUND
............................................................................................................
29
2.2
MARKER-FREE
PARALLELISM
EXISTING
APPROACHES
......................................................
31
2.3
PROPOSED
MARKER-FREE
APPROACH
.........................................................................
33
2.3.1
STATIC
DECODERS
CASE
................................................................................
33
2.3.2
DYNAMIC
DECODERS
CASE
.........................................................................
34
2.4
ARCHITECTURE
OF
MARKER-FREE
PARALLEL
DECODER
...................................................
41
2.4.1
N-SYMBOLS
WIDE
MEMORY
......................................................................
42
2.4.2
N-TO-M
SYMBOL
ADAPTER
.........................................................................
44
2.4.3
PIPELINED
CROSSBAR
.
................................................................................
45
2.4.4
CONTROLLER
...................................................................................................
47
8
CONTENTS
2.5
RESULTS
AND
PERFORMANCE
ANALYSIS
.......................................................................
51
2.5.1
SYSTEM
EFFICIENCY
.......................................................................................
51
2.5.2
SYNTHESIS
RESULTS
.......................................................................................
55
3
PARALLEL
GOLOMB-RICE
DECODER
WITH
ESCAPE
CODES
59
3.1
GOLOMB-RICE
CODES
................................................................................................
60
3.2
PARALLEL
GOLOMB-RICE
DECODING
.............................................................................
61
3.2.1
BASIC
BIT
POSITIONING
................................................................................
61
3.2.2
MODIFIED
BIT
POSITIONING
..........................................................................
62
3.2.3
MODIFIED
BIT
POSITIONING
WITH
ESCAPE
CODES
..........................................
63
3.3
PARALLEL
GOLOMB-RICE
DECODER
ARCHITECTURE
......................................................
64
3.3.1
DELIMITER
INSERTION
...................................................................................
67
3.3.2
SELECTOR
FSM
.............................................................................................
68
3.3.3
SYMBOL
BUILDER
GR/ESC
.............................................................................
70
3.3.4
ALIGNMENT
BLOCK
.......................................................................................
73
3.4
EXPERIMENTAL
RESULTS
.............................................................................................
75
3.4.1
COMPARISON
WITH
THE
BIT
POSITIONING
METHOD
......................................
76
4
REGION-BASED
FILTERING
81
4.1
REGION-BASED
SVD
FILTERING
...................................................................................
85
4.2
HARDWARE
ARCHITECTURE
..........................................................................................
88
4.2.1
ROW
BUFFERS
AND
REWINDER
......................................................................
89
4.2.2
SVD
FILTERING
.............................................................................................
91
4.2.3
COEFFICIENTS
MEMORY
................................................................................
93
4.2.4
INDEXER
......................................................................................................
96
4.3
EVALUATION
OF
THE
PROPOSED
APPROACH
.......................................................................
103
5
CASE
STUDY
ON
REGION-BASED
FILTERING
107
5.1
TELECENTRIC
IMAGING
....................................................................................................
109
5.2
OPTICAL
SETUP
-
DESIGN
..............................................................................................
110
5.3
OPTICAL
SETUP
-
REALIZATION
.......................................................................................
112
5.4
REGION
BASED
WIENER
FILTERING
.................................................................................
115
CONTENTS
9
5.5
EXPERIMENTAL
RESULTS
.................................................................................................
116
5.5.1
QUALITY
ASSESSMENT
.......................................................................................
116
5.5.2
HARDWARE
RESULTS
..........................................................................................
120
5.5.3
WORD-LENGTH
CONSIDERATIONS
.......................................................................
122
5.5.4
COMPARISON
....................................................................................................
123
6
CONCLUSION
125
|
| adam_txt |
C
ONTENTS
LIST
OF
FIGURES
11
LIST
OF
TABLES
15
LIST
OF
ABBREVIATIONS
17
1
INTRODUCTION
19
1.1
REGION-BASED
PARALLEL
ENCODING/DECODING
.
21
1.2
REGION-BASED
IMAGE
FILTERING
.
24
1.3
CONTRIBUTIONS
.
26
2
MARKER-FREE
PARALLEL
DECODING
29
2.1
BACKGROUND
.
29
2.2
MARKER-FREE
PARALLELISM
EXISTING
APPROACHES
.
31
2.3
PROPOSED
MARKER-FREE
APPROACH
.
33
2.3.1
STATIC
DECODERS
CASE
.
33
2.3.2
DYNAMIC
DECODERS
CASE
.
34
2.4
ARCHITECTURE
OF
MARKER-FREE
PARALLEL
DECODER
.
41
2.4.1
N-SYMBOLS
WIDE
MEMORY
.
42
2.4.2
N-TO-M
SYMBOL
ADAPTER
.
44
2.4.3
PIPELINED
CROSSBAR
.
.
45
2.4.4
CONTROLLER
.
47
8
CONTENTS
2.5
RESULTS
AND
PERFORMANCE
ANALYSIS
.
51
2.5.1
SYSTEM
EFFICIENCY
.
51
2.5.2
SYNTHESIS
RESULTS
.
55
3
PARALLEL
GOLOMB-RICE
DECODER
WITH
ESCAPE
CODES
59
3.1
GOLOMB-RICE
CODES
.
60
3.2
PARALLEL
GOLOMB-RICE
DECODING
.
61
3.2.1
BASIC
BIT
POSITIONING
.
61
3.2.2
MODIFIED
BIT
POSITIONING
.
62
3.2.3
MODIFIED
BIT
POSITIONING
WITH
ESCAPE
CODES
.
63
3.3
PARALLEL
GOLOMB-RICE
DECODER
ARCHITECTURE
.
64
3.3.1
DELIMITER
INSERTION
.
67
3.3.2
SELECTOR
FSM
.
68
3.3.3
SYMBOL
BUILDER
GR/ESC
.
70
3.3.4
ALIGNMENT
BLOCK
.
73
3.4
EXPERIMENTAL
RESULTS
.
75
3.4.1
COMPARISON
WITH
THE
BIT
POSITIONING
METHOD
.
76
4
REGION-BASED
FILTERING
81
4.1
REGION-BASED
SVD
FILTERING
.
85
4.2
HARDWARE
ARCHITECTURE
.
88
4.2.1
ROW
BUFFERS
AND
REWINDER
.
89
4.2.2
SVD
FILTERING
.
91
4.2.3
COEFFICIENTS
MEMORY
.
93
4.2.4
INDEXER
.
96
4.3
EVALUATION
OF
THE
PROPOSED
APPROACH
.
103
5
CASE
STUDY
ON
REGION-BASED
FILTERING
107
5.1
TELECENTRIC
IMAGING
.
109
5.2
OPTICAL
SETUP
-
DESIGN
.
110
5.3
OPTICAL
SETUP
-
REALIZATION
.
112
5.4
REGION
BASED
WIENER
FILTERING
.
115
CONTENTS
9
5.5
EXPERIMENTAL
RESULTS
.
116
5.5.1
QUALITY
ASSESSMENT
.
116
5.5.2
HARDWARE
RESULTS
.
120
5.5.3
WORD-LENGTH
CONSIDERATIONS
.
122
5.5.4
COMPARISON
.
123
6
CONCLUSION
125 |
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| author | Baroud, Yousef |
| author_GND | (DE-588)1200899105 |
| author_facet | Baroud, Yousef |
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| bvnumber | BV046671912 |
| classification_rvk | ST 284 |
| ctrlnum | (OCoLC)1143315239 (DE-599)KXP1683952170 |
| discipline | Informatik |
| discipline_str_mv | Informatik |
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| id | DE-604.BV046671912 |
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| index_date | 2024-07-03T14:21:32Z |
| indexdate | 2024-07-10T08:50:52Z |
| institution | BVB |
| language | English German |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-032082896 |
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| physical | 141 Seiten Illustrationen, Diagramme 21 cm |
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| spelling | Baroud, Yousef Verfasser (DE-588)1200899105 aut Memory efficient hardware architectures for data compression and reduction in the parallel image processing domain vorgelegt von Yousef Baroud Stuttgart 2019 141 Seiten Illustrationen, Diagramme 21 cm txt rdacontent n rdamedia nc rdacarrier Dissertation Universität Stuttgart 2019 Datenkompression (DE-588)4121121-2 gnd rswk-swf Parallelverarbeitung (DE-588)4075860-6 gnd rswk-swf Bildverarbeitung (DE-588)4006684-8 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Datenkompression (DE-588)4121121-2 s Bildverarbeitung (DE-588)4006684-8 s Parallelverarbeitung (DE-588)4075860-6 s DE-604 V:DE-603;B:DE-17 application/pdf http://scans.hebis.de/HEBCGI/show.pl?46056237_toc.pdf Inhaltsverzeichnis DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=032082896&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Baroud, Yousef Memory efficient hardware architectures for data compression and reduction in the parallel image processing domain Datenkompression (DE-588)4121121-2 gnd Parallelverarbeitung (DE-588)4075860-6 gnd Bildverarbeitung (DE-588)4006684-8 gnd |
| subject_GND | (DE-588)4121121-2 (DE-588)4075860-6 (DE-588)4006684-8 (DE-588)4113937-9 |
| title | Memory efficient hardware architectures for data compression and reduction in the parallel image processing domain |
| title_auth | Memory efficient hardware architectures for data compression and reduction in the parallel image processing domain |
| title_exact_search | Memory efficient hardware architectures for data compression and reduction in the parallel image processing domain |
| title_exact_search_txtP | Memory efficient hardware architectures for data compression and reduction in the parallel image processing domain |
| title_full | Memory efficient hardware architectures for data compression and reduction in the parallel image processing domain vorgelegt von Yousef Baroud |
| title_fullStr | Memory efficient hardware architectures for data compression and reduction in the parallel image processing domain vorgelegt von Yousef Baroud |
| title_full_unstemmed | Memory efficient hardware architectures for data compression and reduction in the parallel image processing domain vorgelegt von Yousef Baroud |
| title_short | Memory efficient hardware architectures for data compression and reduction in the parallel image processing domain |
| title_sort | memory efficient hardware architectures for data compression and reduction in the parallel image processing domain |
| topic | Datenkompression (DE-588)4121121-2 gnd Parallelverarbeitung (DE-588)4075860-6 gnd Bildverarbeitung (DE-588)4006684-8 gnd |
| topic_facet | Datenkompression Parallelverarbeitung Bildverarbeitung Hochschulschrift |
| url | http://scans.hebis.de/HEBCGI/show.pl?46056237_toc.pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=032082896&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT baroudyousef memoryefficienthardwarearchitecturesfordatacompressionandreductionintheparallelimageprocessingdomain |
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