Interaction of hardware transactional memory and microprocessor microarchitecture:
Microprocessors have experienced a significant stall in single-thread performance since about 2004. Instead of significant annual performance improvements for a single core, it is easier to increase performance by providing multiple, independent cores that the application programmer has to coordinat...
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| Zusammenfassung: | Microprocessors have experienced a significant stall in single-thread performance since about 2004. Instead of significant annual performance improvements for a single core, it is easier to increase performance by providing multiple, independent cores that the application programmer has to coordinate. Exposing concurrency to the applications requires mechanisms to control it. Hardware Transactional Memory (HTM) is an abstraction that provides optimistic, fine-grained concurrency control with a simple application interface, and has received significant research attentions fro 2004 - 2010, with initial publications in the mid-90s. The central thesis of my work is that detailed analysis and ISA modelling of HTM is necessary to understand actual implementation and usage challenges, and get more realistic results. Instead of overly complicating the design of HTM with features that would be extremely hard to implement right in a more detailed microarchitecture and ISA proposal, I suggest that getting a base-line HTM specification and micro-architecture right is a challenge in itself. Yet, despite the complexity, there are interesting implementation options and extensions that can provide benefits to applications using HTM–but they are not on the trajectory taken by most papers published between 2004 and 2010. |
| Beschreibung: | Enthält 7 Papers |
| Beschreibung: | xi, 317 Seiten Illustrationen, Diagramme 30 cm |
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| 100 | 1 | |a Diestelhorst, Stephan |d 1981- |e Verfasser |0 (DE-588)1191281272 |4 aut | |
| 245 | 1 | 0 | |a Interaction of hardware transactional memory and microprocessor microarchitecture |c by Stephan Diestelhorst |
| 264 | 1 | |a Dresden |c 9th June 2019 | |
| 300 | |a xi, 317 Seiten |b Illustrationen, Diagramme |c 30 cm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
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| 500 | |a Enthält 7 Papers | ||
| 502 | |b Dissertation |c Technische Universität Dresden |d 2019 | ||
| 520 | 3 | |a Microprocessors have experienced a significant stall in single-thread performance since about 2004. Instead of significant annual performance improvements for a single core, it is easier to increase performance by providing multiple, independent cores that the application programmer has to coordinate. Exposing concurrency to the applications requires mechanisms to control it. Hardware Transactional Memory (HTM) is an abstraction that provides optimistic, fine-grained concurrency control with a simple application interface, and has received significant research attentions fro 2004 - 2010, with initial publications in the mid-90s. The central thesis of my work is that detailed analysis and ISA modelling of HTM is necessary to understand actual implementation and usage challenges, and get more realistic results. Instead of overly complicating the design of HTM with features that would be extremely hard to implement right in a more detailed microarchitecture and ISA proposal, I suggest that getting a base-line HTM specification and micro-architecture right is a challenge in itself. Yet, despite the complexity, there are interesting implementation options and extensions that can provide benefits to applications using HTM–but they are not on the trajectory taken by most papers published between 2004 and 2010. | |
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| 653 | |a Computer Architecture, Synchronisation, Multi-Core, SMP, Transactional Memory | ||
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Datensatz im Suchindex
| _version_ | 1804180801844150272 |
|---|---|
| adam_text | CONTENTS
LIST
OF
FIGURES
VII
LIST
OF
TABLES
IX
1
INTRODUCTION
1
1.1
CONTEXT
1
1.2
TRANSACTIONAL
MEMORY
1.3
THESIS
1.4
CONTRIBUTIONS
1.5
TERMINOLOGY
1.6
OUTLINE
2
OVERVIEW
AND
RELATED-WORK
2.1
INTRODUCTION
2.1.1
BASICS
AND
BEGINNINGS
2.1.2
SPECULATIVE
SYNCHRONISATION
2.1.3
CREATIVE
EXPLOSION
2.1.4
ORGANISATION
2.2
TRANSACTIONAL
MEMORY
RESEARCH
2.2.1
SOFTWARE
TRANSACTIONAL
MEMORY
2.2.2
LOCK
ELISION
AND
THREAD-LEVEL
SPECULATION
2.2.3
HARDWARE
TRANSACTIONAL
MEMORY
2.2.4
TRANSACTIONS
AS
STANDARD
SYNCHRONISATION
PRIMITIVE
2.2.5
VIRTUALISING
TRANSACTIONAL
MEMORY
2.2.6
IMPROVING
COMMIT
PATH
PERFORMANCE
-
EAGER
LOGGING
UNBOUNDED
TM
2.2.7
MICRO-ARCHITECTURE
OF
TRANSACTIONAL
MEMORY
IMPLEMENTATIONS
2.2.8
INSTRUCTION-SET
DESIGN
FOR
HARDWARE
TRANSACTIONAL
MEMORY
2.2.9
OTHER
CONCERNS:
ENERGY
AND
GPUS
2.2.10
ENHANCING
TRANSACTIONS
2.2.11
HYBRID
TRANSACTIONAL
MEMORY
2.2.12
COMPOSITE
TRANSACTIONAL
MEMORY
2.2.13
CONCEPTS
AND
THEORY
OF
TM
2.3
INDUSTRY
ADOPTION
2.3.1
EARLY
INDUSTRY
APPROACHES
2.3.2
FIRST
INDUSTRIAL
SILICON:
SUN
ROCK
AND
AZUL
2.3.3
IBM
*
S
HTM:
A
BOUQUET
OF
ARCHITECTURES
AND
MICROARCHITECTURES
2.3.4
INTEL
TSX:
(SEMI-)TRANSPARENT
HARDWARE
LOCK
ELISION
2.3.5
COMPARISON
OF
COMMERCIAL
HTMS
2.4
TRANSACTIONAL
MEMORY
USE-CASES
2.4.1
ALGORITHMS
AND
MICRO-BENCHMARKS
2.4.2
OTHER
USE
CASES
2.4.3
LANGUAGE
SUPPORT
2.4.4
BENCHMARK
SUITES
2.4.5
APPLICATION
STUDIES
2.4.6
TRANSACTIONS
AND
OPERATING
SYSTEMS
2.5
BACKGROUND
III
IV
CONTENTS
2.5.1
CPU
ARCHITECTURE
AND
MICRO-ARCHITECTURE
........................................................................
49
2.5.2
SIMULATION
..........................................................................................................................
50
2.6
SUMMARY
.........................................................................................................................................
53
2.6.1
HTM
SUMMARY
....................................................................................................................
53
2.6.2
COMPUTER
ARCHITECTURE
AND
SIMULATION
...........................................................................
54
3
INSTRUCTION-SET
ARCHITECTURE
AND
HIGH-LEVEL
DESIGN
OF
HTM
57
3.1
INTRODUCTION
.......................................................................................................................................
57
3.1.1
ARCHITECTURAL
CONCEPTS
AND
FUNCTIONALITY
OF
HTM
.........................................................
58
3.2
HTM
INSTRUCTION
SET
ARCHITECTURE
DESIGN
.....................................................................................
59
3.2.1
ASF
1:
A
PRECURSOR TO
FULL
BEHTM
..................................................................................
59
3.2.2
ASF
2:
AMD
*
S
HARDWARE
TRANSACTIONAL
MEMORY
PROPOSAL
............................................
60
3.2.3
CONFLICT
DETECTION
AND
TRANSACTION
ABORTS
.....................................................................
60
3.2.4
NESTING
OF
TRANSACTIONS
....................................................................................................
62
3.2.5
NON-TRANSACTIONAL
MEMORY
ACCESSES
..............................................................................
62
3.2.6
NON-TRANSACTIONAL
ACCESS
CHALLENGES
..............................................................................
63
3.2.7
LIMITED
REGISTER
CHECKPOINTING
........................................................................................
65
3.2.8
INTERACTIONS
WITH
THE
MEMORY
MODEL
..............................................................................
66
3.2.9
INSTRUCTION
SUPPORT
AND
NON-CONFLICT
SOURCES
OF
ABORTS
............................................
67
3.3
LANGUAGE
INTEGRATION
PROTOTYPE
....................................................................................................
68
3.4
INCREMENTAL
ADAPTATIONS
OF
ASF
....................................................................................................
72
3.4.1
INVERTED
TRANSACTIONAL
SEMANTICS
.....................................................................................
72
3.4.2
SIGNALLING
TRANSACTIONAL
PROBLEMS
..................................................................................
73
3.5
CAPACITY
AND
ARCHITECTURAL
PROGRESS
..............................................................................................
74
3.6
SUMMARY
..........................................................................................................................................
75
4
MICROARCHITECTURAL
IMPLEMENTATION
DETAILS
OF
HTM
77
4.1
INTRODUCTION
.......................................................................................................................................
78
4.1.1
PROCESSOR
MICROARCHITECTURE
..............................................................................................
78
4.1.2
RECOVERY
FROM
OUT-OF-ORDER
MISSPECULATION
..................................................................
80
4.1.3
COHERENCY
PROTOCOL
BASICS
.................................................................................................
81
4.2
KEY
MICROARCHITECTURAL
HTM
MECHANISMS
..................................................................................
81
4.2.1
DATA
VERSIONING
....................................................................................................................
81
4.2.2
CONFLICT
DETECTION
..............................................................................................................
83
4.2.3
MULTI-WORD
ATOMIC
STORE
VISIBILITY
..................................................................................
84
4.2.4
ROLLBACK
OF
TRANSACTIONAL
STATE
........................................................................................
86
4.3
BASIC
IMPLEMENTATION
VARIANTS
........................................................................................................
87
4.3.1
SPECULATION
MECHANISM
REUSE
...........................................................................................
87
4.3.2
CACHE-BASED
IMPLEMENTATION
...........................................................................................
88
4.3.3
LLB-BASED
IMPLEMENTATION
..............................................................................................
88
4.4
BASIC
PIPELINE
AND
OUT-OF-ORDER
CORE
INTEGRATION
.....................................................................
88
4.4.1
SEQUENTIAL
ASF
SEMANTICS
.................................................................................................
88
4.4.2
SPECULATIVE-REGION
FLOW
....................................................................................................
89
4.4.3
MISSPECULATION
....................................................................................................................
91
4.4.4
ABORT
SEMANTICS
.................................................................................................................
93
4.4.5
CONFLICT
DETECTION
HANDSHAKE
...........................................................................................
93
4.4.6
ABORT
MECHANICS
AND
IMPLICATIONS
..................................................................................
95
4.4.7
CAPACITY
GUARANTEES
...........................................................................................................
97
4.5
ENHANCED
PIPELINE
INTEGRATION
.......................................................................................................
98
4.5.1
OVERVIEW
.............................................................................................................................
98
4.5.2
EXTENDED
TRANSACTIONAL
INSTRUCTION
IMPLEMENTATION
.....................................................
99
4.5.3
ENHANCED
TRANSACTIONAL
FLOWS
..............................................................................................
102
4.5.4
EARLY
RELEASE
OF
TRANSACTIONAL
DATA
.....................................................................................
106
4.6
ALTERNATIVE
MICROARCHITECTURAL
IMPLEMENTATION
VARIANTS
...............................................................
106
4.6.1
AMD
BULLDOZER
MICROARCHITECTURE
INTEGRATION
SKETCH
.....................................................
106
4.6.2
PIPELINE-ONLY
IMPLEMENTATION
..............................................................................................
107
4.7
HIGH-LEVEL
INTERACTION
BETWEEN
MICROARCHITECTURE
AND
HTM
.....................................................
107
4.7.1
VISIBLE
MICROARCHITECTURE
ARTIFACTS
....................................................................................
108
CONTENTS
V
4.7.2
PROGRESS
...................................................................................................................................
108
4.7.3
INFLUENCE
OF
ASF-SPECIFIC
FEATURES
.......................................................................................
110
4.8
SUMMARY
............................................................................................................................................
110
5
APPLICATIONS
AND
EVALUATION
OF
HTM
113
5.1
INTRODUCTION
.........................................................................................................................................
113
5.2
APPLICATIONS
OF
HTM
..........................................................................................................................
114
5.2.1
DIRECT
HTM
USAGE
................................................................................................................
114
5.2.2
LOCK
ELISION
.............................................................................................................................
116
5.2.3
SUMMARY:
CHALLENGES
OF
LOCK
ELISION
.................................................................................
119
5.3
EVALUATION
EXPERIMENTS
...................................................................................................................
120
5.3.1
INTEGER
SET
DATA
STRUCTURES
.................................................................................................
120
5.3.2
STAMP:
COMPLEX
WORKLOADS
.................................................................................................
124
5.3.3
MEMCACHED:
ELISION
AND
TRANSACTION
CHARACTERISTICS
........................................................
129
5.3.4
EVALUATION
SUMMARY
.............................................................................................................
129
5.4
SIMULATOR
IMPLEMENTATION
DETAILS
....................................................................................................
132
5.4.1
CHARACTERISTICS
OF
CYCLE-LEVEL
SIMULATOR
ENVIRONMENTS
.................................................. 133
5.4.2
ASF
SIMULATOR
IMPLEMENTATION
..........................................................................................
139
5.4.3
SIMPLIFICATIONS
.......................................................................................................................
148
5.4.4
SIMULATOR
EXTENSIONS
AND
COMPLICATIONS
...........................................................................
149
5.5
SUMMARY
.............................................................................................................................................
151
6
EXTENSIONS
AND
NEW
USE-CASES
153
6.1
INTRODUCTION
.........................................................................................................................................
153
6.2
AD-HOC
COMMUNICATING
HARDWARE
TRANSACTIONS
...........................................................................
153
6.3
STRUCTURED
COMMUNICATION:
DELEGATION
AND
NESTING
IN
BEST-EFFORT
HTM
...............................
154
6.3.1
TRANSACTIONAL
CHANNELS
.......................................................................................................
155
6.3.2
COMMUNICATION
PATTERNS
.......................................................................................................
155
6.3.3
ABORTS
DURING
CHANNEL
OPERATION
.......................................................................................
157
6.3.4
USE
CASE:
MEMORY
ALLOCATION
..............................................................................................
157
6.4
BETWEEN
ALL
AND
NOTHING-VERSATILE
ABORTS
IN
HARDWARE
TRANSACTIONAL
MEMORY
......................
158
6.4.1
CHALLENGES
.............................................................................................................................
160
6.4.2
USE-CASES
OF
TRANSACTIONAL
RESURRECTION
...........................................................................
160
6.4.3
WORKING
SET
HANDLING
..........................................................................................................
163
6.4.4
EVALUATION
................................................................................................................................
164
6.5
SUMMARY
............................................................................................................................................
167
7
OUTLOOK:
SEMANTIC
CHALLENGES
AND
FURTHER
ARCHITECTURAL
IMPROVEMENT
OPPORTUNITIES
169
7.1
INTRODUCTION
.........................................................................................................................................
169
7.2
DECOMPOSING
HTM
AND
LOCK
ELISION
PRIMITIVES
...........................................................................
169
7.3
SAFELY
ACCESSING
TIMESTAMPS
IN
TRANSACTIONS
.................................................................................
171
7.3.1
BACKGROUND
.............................................................................................................................
172
7.3.2
SEMANTICS
OF
TIME
STAMPS
....................................................................................................
172
7.3.3
SEMANTIC
ISSUES
OF
TIME
STAMPS
IN
TRANSACTIONS
..............................................................
174
7.3.4
SUPPORTING
TIME
STAMPS
IN
TRANSACTIONS
...........................................................................
176
7.3.5
OUTLOOK
...................................................................................................................................
178
7.3.6
CONCLUSION
.............................................................................................................................
178
7.4
FURTHER
HTM
IDEAS
.............................................................................................................................
179
7.4.1
ROLL-FORWARD
MODE
................................................................................................................
179
7.4.2
NESTED
ABORT
HANDLERS
..........................................................................................................
179
7.4.3
TWO-DIMENSIONAL
TRACKING
OF
LARGE
OBJECTS
.....................................................................
180
7.4.4
TRACKING
LARGE
OBJECTS
IN
THE
TLB
/
PAGE
TABLES
..............................................................
181
7.4.5
REDUCING
LIVE-LOCK
BY
ORDERING
TRANSACTION
MEMORY
ACCESSES
......................................181
7.5
HTM
PRODUCT
EXPERIENCES
................................................................................................................
181
7.6
SUMMARY
............................................................................................................................................
183
VI
CONTENTS
8
CONCLUSIONS
185
8.1
SUMMARY
.............................................................................................................................................
185
8.2
THESIS
EVALUATION
.................................................................................................................................
186
8.3
CRITICAL
REFLECTION
.................................................................................................................................
187
8.4
CURRENT
STATE
OF
THE
ECO-SYSTEM
........................................................................................................
188
8.5
POST-THESIS
WORK
....................................................................................................................................
189
BIBLIOGRAPHY
191
A
ASF
2.0
SPECIFICATION
225
A.1
INTRODUCTION
.........................................................................................................................................
232
A.2
TERMINOLOGY
.........................................................................................................................................
238
A.3
CPUID
IDENTIFICATION
.........................................................................................................................
241
A.
4
MODEL-SPECIFIC
REGISTERS
...................................................................................................................
243
A.
5
INSTRUCTIONS
.........................................................................................................................................
245
A.
6
OPERATION
IN
ASF
SPECULATIVE
REGIONS
.............................................................................................
254
A.
7
ASF
USAGE
MODELS
............................................................................................................................
262
B
WORKSHOP
PAPERS
269
B.
1
EPHAM
2008:
HARDWARE
ACCELERATION
FOR
LOCK-FREE
DATA
STRUCTURES
AND
SOFTWARE-TRANSACTIONAL
MEMORY
................................................................................................................................................
270
B.2
TRANSACT
2010:
IMPLEMENTING
AMD
*
S
ADVANCED
SYNCHRONIZATION
FACILITY
IN
AN
OUT-OF-
ORDER
X86
CORE
....................................................................................................................................
278
B.3
TRANSACT
2010:
COMPILATION
OF
THOUGHTS
ABOUT
AMD
ADVANCED
SYNCHRONIZATION
FACILITY
AND
FIRST-GENERATION
HARDWARE TRANSACTIONAL
MEMORY
SUPPORT
...............................................
286
B.4
TRANSACT
2011:
FROM
LIGHTWEIGHT
HARDWARE
TRANSACTIONAL
MEMORY
TO
LIGHTWEIGHT
LOCK
ELISION
...................................................................................................................................................
293
B.5
WTTM
2010:
SANE
SEMANTICS
OF
BEST-EFFORT
HARDWARE
TRANSACTIONAL
MEMORY
......................
300
B.6
WTTM
2012:
SAFELY
ACCESSING
TIME
STAMPS
IN
TRANSACTIONS
.....................................................
304
B.7
TRANSACT
2015:
BETWEEN
ALL
AND
NOTHING-VERSATILE
ABORTS
IN
HARDWARE
TRANSACTIONAL
MEMORY
................................................................................................................................................
308
|
| any_adam_object | 1 |
| author | Diestelhorst, Stephan 1981- |
| author_GND | (DE-588)1191281272 |
| author_facet | Diestelhorst, Stephan 1981- |
| author_role | aut |
| author_sort | Diestelhorst, Stephan 1981- |
| author_variant | s d sd |
| building | Verbundindex |
| bvnumber | BV046320166 |
| ctrlnum | (OCoLC)1135657132 (DE-599)DNB1190826852 |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Thesis Book |
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| genre_facet | Hochschulschrift |
| id | DE-604.BV046320166 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T08:41:32Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-031697201 |
| oclc_num | 1135657132 |
| open_access_boolean | |
| owner | DE-83 |
| owner_facet | DE-83 |
| physical | xi, 317 Seiten Illustrationen, Diagramme 30 cm |
| publishDate | 2019 |
| publishDateSearch | 2019 |
| publishDateSort | 2019 |
| record_format | marc |
| spelling | Diestelhorst, Stephan 1981- Verfasser (DE-588)1191281272 aut Interaction of hardware transactional memory and microprocessor microarchitecture by Stephan Diestelhorst Dresden 9th June 2019 xi, 317 Seiten Illustrationen, Diagramme 30 cm txt rdacontent n rdamedia nc rdacarrier Enthält 7 Papers Dissertation Technische Universität Dresden 2019 Microprocessors have experienced a significant stall in single-thread performance since about 2004. Instead of significant annual performance improvements for a single core, it is easier to increase performance by providing multiple, independent cores that the application programmer has to coordinate. Exposing concurrency to the applications requires mechanisms to control it. Hardware Transactional Memory (HTM) is an abstraction that provides optimistic, fine-grained concurrency control with a simple application interface, and has received significant research attentions fro 2004 - 2010, with initial publications in the mid-90s. The central thesis of my work is that detailed analysis and ISA modelling of HTM is necessary to understand actual implementation and usage challenges, and get more realistic results. Instead of overly complicating the design of HTM with features that would be extremely hard to implement right in a more detailed microarchitecture and ISA proposal, I suggest that getting a base-line HTM specification and micro-architecture right is a challenge in itself. Yet, despite the complexity, there are interesting implementation options and extensions that can provide benefits to applications using HTM–but they are not on the trajectory taken by most papers published between 2004 and 2010. Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Synchronisierung (DE-588)4130847-5 gnd rswk-swf Mehrkernprozessor (DE-588)7598578-0 gnd rswk-swf Computer Architecture, Synchronisation, Multi-Core, SMP, Transactional Memory Computerarchitektur, Synchronisation, Multi-Core, SMP, Transaktionsspeicher info:eu-repo/classification/ddc/004 ddc:004 info:eu-repo/semantics/publishedVersion doc-type:doctoralThesis info:eu-repo/semantics/doctoralThesis doc-type:Text (DE-588)4113937-9 Hochschulschrift gnd-content Computerarchitektur (DE-588)4048717-9 s Synchronisierung (DE-588)4130847-5 s Mehrkernprozessor (DE-588)7598578-0 s DE-604 B:DE-101 application/pdf http://d-nb.info/1190826852/04 Inhaltsverzeichnis DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=031697201&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Diestelhorst, Stephan 1981- Interaction of hardware transactional memory and microprocessor microarchitecture Computerarchitektur (DE-588)4048717-9 gnd Synchronisierung (DE-588)4130847-5 gnd Mehrkernprozessor (DE-588)7598578-0 gnd |
| subject_GND | (DE-588)4048717-9 (DE-588)4130847-5 (DE-588)7598578-0 (DE-588)4113937-9 |
| title | Interaction of hardware transactional memory and microprocessor microarchitecture |
| title_auth | Interaction of hardware transactional memory and microprocessor microarchitecture |
| title_exact_search | Interaction of hardware transactional memory and microprocessor microarchitecture |
| title_full | Interaction of hardware transactional memory and microprocessor microarchitecture by Stephan Diestelhorst |
| title_fullStr | Interaction of hardware transactional memory and microprocessor microarchitecture by Stephan Diestelhorst |
| title_full_unstemmed | Interaction of hardware transactional memory and microprocessor microarchitecture by Stephan Diestelhorst |
| title_short | Interaction of hardware transactional memory and microprocessor microarchitecture |
| title_sort | interaction of hardware transactional memory and microprocessor microarchitecture |
| topic | Computerarchitektur (DE-588)4048717-9 gnd Synchronisierung (DE-588)4130847-5 gnd Mehrkernprozessor (DE-588)7598578-0 gnd |
| topic_facet | Computerarchitektur Synchronisierung Mehrkernprozessor Hochschulschrift |
| url | http://d-nb.info/1190826852/04 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=031697201&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT diestelhorststephan interactionofhardwaretransactionalmemoryandmicroprocessormicroarchitecture |
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