Fundamentals of power semiconductor devices:
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| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Cham
Springer
[2019]
|
| Edition: | Second edition |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | xxxii, 1086 Seiten Illustrationen, Diagramme |
| ISBN: | 9783319939872 |
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MARC
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| 100 | 1 | |a Baliga, B. Jayant |d 1948- |e Verfasser |0 (DE-588)136919014 |4 aut | |
| 245 | 1 | 0 | |a Fundamentals of power semiconductor devices |c B. Jayant Baliga |
| 250 | |a Second edition | ||
| 264 | 1 | |a Cham |b Springer |c [2019] | |
| 300 | |a xxxii, 1086 Seiten |b Illustrationen, Diagramme | ||
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Record in the Search Index
| _version_ | 1804180543242240000 |
|---|---|
| adam_text | B Jayant Baliga
Fundamentals of Power
Semiconductor Devices
Second Edition
*0 Springer
Contents
1 Introduction 1
1 1 Ideal and Typical Power-Switching Waveforms 3
1 2 Ideal and Typical Power Device Characteristics 5
1 3 Unipolar Power Devices 8
1 4 Bipolar Power Devices 10
1 5 MOS-Bipolar Power Devices 10
1 6 Ideal Drift Region for Unipolar Power Devices 14
1 7 Charge-Coupled Structures: Ideal Specific On-Resistance 16
1 8 Summary 20
References 22
2 Material Properties and Transport Physics 23
2 1 Fundamental Properties 23
211 Intrinsic Carrier Concentration 24
212 Bandgap Narrowing 26
213 Built-in Potential 30
214 Zero-Bias Depletion Width 32
215 Impact Ionization Coefficients 32
216 Carrier Mobility 35
2 2 Resistivity 51
221 Intrinsic Resistivity 51
222 Extrinsic Resistivity 51
223 Neutron Transmutation Doping 54
2 3 Recombination Lifetime 59
231 Shockley-Read-Hall Recombination 60
232 Low-Level Lifetime 63
233 Space-Charge Generation Lifetime 64
234 Recombination Level Optimization 66
xix
XX
Contents
235 Lifetime Control 75
236 Auger Recombination 80
2 4 Ohmic Contacts 82
2 5 Summary 83
References 85
3 Breakdown Voltage 89
3 1 Avalanche Breakdown 90
311 Power Law Approximations for the Impact
Ionization Coefficients 90
312 Multiplication Coefficient 92
3 2 Abrupt One-Dimensional Diode 94
321 Temperature Dependence 99
3 3 Ideal Specific On-Resistance 99
3 4 Abrupt Punch-Through Diode 100
3 5 Linearly Graded Junction Diode 102
3 6 Edge Terminations 106
361 Planar Junction Termination 106
362 Planar Junction with Floating Field Ring 119
363 Planar Junction with Multiple Floating Field
Rings 129
364 Planar Junction with Field Plate 131
365 Planar Junction with Field Plates and Field
Rings 136
366 Bevel Edge Terminations 136
367 Etch Terminations 147
368 Junction Termination Extension 148
3 7 Open-Base Transistor Breakdown 153
371 Composite Bevel Termination 158
372 Double-Positive Bevel Termination 159
3 8 Surface Passivation 161
3 9 Silicon Carbide Edge Terminations 162
391 Argon-Implanted Edge Termination 162
392 Multiple-Floating-Zone Junction Termination
Extension 163
393 Hybrid Junction Termination Extension 163
394 Multiple Floating Field Ring Design 164
395 Orthogonal Positive Bevel Termination 166
3 10 Summary 167
References 168
4 Schottky Rectifiers 171
4 1 Power Schottky Rectifier Structure 172
4 2 Metal-Semiconductor Contact 173
4 3 Forward Conduction 175
Contents xxi
4 4 Reverse Blocking 183
441 Leakage Current 184
442 Schottky Barrier Lowering 185
443 Pre-breakdown Avalanche Multiplication 188
444 Silicon Carbide Rectifiers 189
4 5 Device Capacitance 191
4 6 Thermal Considerations 192
4 7 Fundamental Trade-Off Analysis 196
4 8 Device Technology 198
4 9 Barrier Height Adjustment 199
4 10 Edge Terminations 201
4 11 Reverse Recovery Current 202
4 12 Summary 203
References 206
5 P-i-N Rectifiers 207
5 1 One-Dimensional Structure 208
511 Recombination Current 209
512 Low-Level Injection Current 210
513 High-Level Injection Current 212
514 Injection into the End Regions 221
515 Carrier-Carrier Scattering Effect 223
516 Auger Recombination Effect 223
517 Forward Conduction Characteristics 225
5 2 Silicon Carbide P-i-N Rectifiers 234
5 3 Reverse Blocking 236
5 4 Switching Performance 240
541 Forward Recovery 240
542 Reverse Recovery 247
5 5 P-i-N Rectifier Structure with Buffer Layer 265
5 6 Non-Punch-Through P-i-N Rectifier Structure 266
5 7 P-i-N Rectifier Trade-Off Curves 273
571 Lifetime Control 276
5 8 Safe Operating Area 277
5 9 Maximum Allowable [dJ/dl] 279
5 10 Summary 280
References 281
6 Power MOSFETs 283
6 1 Ideal Specific On-Resistance 284
6 2 Device Cell Structure and Operation 286
621 The V-MOSFET Structure 287
622 The VD-MOSFET Structure 288
623 The U-MOSFET Structure 289
6 3 Basic Device Characteristics 291
xxii Contents
6 4 Blocking Voltage 293
641 Impact of Edge Termination 294
642 Impact of Graded Doping Profile 295
643 Impact of Parasitic Bipolar Transistor 296
644 Impact of Cell Pitch 297
645 Impact of Gate Shape 200
646 Impact of Cell Surface Topology 203
6 5 Forward Conduction Characteristics 205
651 MOS Interface Physics 205
652 MOS Surface Charge Analysis 209
653 Maximum Depletion Width 214
654 Threshold Voltage 216
655 Channel Resistance 226
6 6 Power VD-MOSFET On-Resistance 231
661 Source Contact Resistance 234
662 Source Region Resistance 235
663 Channel Resistance 236
664 Accumulation Resistance 237
665 JFET Resistance 238
666 Drift Region Resistance 239
667 FT Substrate Resistance 244
668 Drain Contact Resistance 244
669 Total On-Resistance 245
6 7 Power VD-MOSFET Cell Optimization 248
671 Optimization of Gate Electrode Width 248
672 Impact of Breakdown Voltage 250
673 Impact of Design Rules 253
674 Impact of Cell Topology 255
6 8 Power U-MOSFET On-Resistance 263
681 Source Contact Resistance 264
682 Source Region Resistance 266
683 Channel Resistance 266
684 Accumulation Resistance 267
685 Drift Region Resistance 268
686 N* Substrate Resistance 270
687 Drain Contact Resistance 270
688 Total On-Resistance 270
6 9 Power U-MOSFET Cell Optimization 273
691 Orthogonal P-Base Contact Structure 273
692 Impact of Breakdown Voltage 275
693 Ruggedness Improvement 277
6 10 Square-Law Transfer Characteristics 278
6 11 Superlinear Transfer Characteristics 3
6 12 Output Characteristics 287
Contents
xxm
6 13 Device Capacitances 391
6 13 1 Basic MOS Capacitance 391
6 13 2 Power VD-MOSFET Structure Capacitances 394
6 13 3 Power U-MOSFET Structure Capacitances 403
6 13 4 Equivalent Circuit 413
6 14 Gate Charge 414
6 14 1 Charge Extraction 415
6 14 2 Voltage and Current Dependence 422
6 14 3 VD-MOSFET Versus U-MOSFET Structure 425
6 14 4 Impact of VD-MOSFET and U-MOSFET
Cell Pitch 428
6 15 Optimization for High-Frequency Operation 432
6 15 1 Input Switching Power Loss 432
6 15 2 Output Switching Power Loss 438
6 15 3 Gate Propagation Delay 440
6 16 Switching Characteristics 441
6 16 1 Tum-On Transient 443
6 16 2 Tum-Off Transient 446
6 16 3 Switching Power Losses 448
6 16 4 [dV/dt] Capability 449
6 17 Safe Operating Area 453
6 17 1 Bipolar Second Breakdown 455
6 17 2 MOS Second Breakdown 457
6 18 Integral Body Diode 458
6 18 1 Reverse Recovery Enhancement 459
6 18 2 Impact of Parasitic Bipolar Transistor 460
6 19 High-Temperature Characteristics 460
6 19 1 Threshold Voltage 461
6 19 2 On-Resistance 462
6 19 3 Saturation Transconductance 463
6 20 Complementary Devices 464
6 20 1 P-channel Structure 464
6 20 2 On-Resistance 465
6 20 3 Deep-Trench Structure 465
6 21 Silicon Power MOSFET Process Technology 466
6 21 1 Planar VD-MOSIET Process 466
6 21 2 Trench U-MOSFET Process 469
6 22 Silicon Carbide Devices 471
6 22 1 The Baliga-Pair Configuration 471
6 22 2 Planar Power MOSFET Structure 482
6 22 3 Shielded Planar Power MOSFET Structures 488
6 22 4 Shielded Trench-Gate Power MOSFET Structure 496
6 22 5 JBSFET Structure 506
6 22 6 Bidirectional Field-Effect Transistor 507
xxiv Contents
6 23 Unclamped Inductive Load Tum-Off 511
6 24 Summary 514
References 518
7 Bipolar Junction Transistors 521
7 1 Power Bipolar Junction Transistor Structure 522
7 2 Basic Operating Principles 524
7 3 Static Blocking Characteristics 527
731 Open-Emitter Breakdown Voltage 527
732 Open-Base Breakdown Voltage 528
733 Shorted Base-Emitter Operation 530
7 4 Current Gain 533
741 Emitter Injection Efficiency 536
742 Emitter Injection Efficiency with Recombination
in the Depletion Region 540
743 Emitter Injection Efficiency with High-Level
Injection in the Base 541
744 Base Transport Factor 547
745 Base Widening at High Collector Current Density 550
7 5 Emitter Current Crowding 564
751 Low-Level Injection in the Base 565
752 High-Level Injection in the Base 569
753 Emitter Geometry 573
7 6 Output Characteristics 574
7 7 On-State Characteristics 579
771 Saturation Region 581
772 Quasi-Saturation Region 585
7 8 Switching Characteristics 589
781 Turn-On Transition 589
782 Tum-Off Transition 601
7 9 Safe Operating Area 624
791 Forward Biased Second Breakdown 625
792 Reverse Biased Second Breakdown 628
793 Boundary for Safe Operating Area 632
7 10 Darlington Configuration 633
7 11 Summary 636
References 638
8 Thyristors 641
8 1 Power Thyristor Structure and Operation 644
8 2 Blocking Characteristics 648
821 Reverse Blocking Capability 648
822 Forward Blocking Capability 652
823 Cathode Shorting 657
824 Cathode Shorting Geometry 660
Contents
xxv
8 3 On-State Characteristics 667
831 On-State Operation 669
832 Gate Triggering Current 671
833 Holding Current 674
8 4 Switching Characteristics 679
841 Turn-On Time 679
842 Gate Design 688
843 Amplifying Gate Design 689
844 [dV/dt] Capability 692
845 Turn-Off Process 699
8 5 Light-Activated Thyristors 702
851 [dlldt] Capability 702
852 Gate Region Design 704
853 Optically Generated Current Density 705
854 Amplifying Gate Design 706
8 6 Self-Protected Thyristors 707
861 Forward Breakdown Protection 707
862 [dV/dt] Tum-On Protection 711
8 7 The Gate Turn-Off Thyristor Structure 714
871 Basic Structure and Operation 715
872 One-Dimensional Tum-Off Criterion 718
873 One-Dimensional Storage Time Analysis 720
874 Two-Dimensional Storage Time Model 720
875 One-Dimensional Voltage Rise-Time Model 722
876 One-Dimensional Current Fall-Time Model 725
877 Switching Energy Loss 737
878 Maximum Tum-Off Current 739
879 Cell Design and Layout 741
8 8 The Triac Structure 743
881 Basic Structure and Operation 744
882 Gate Triggering Mode 1 747
883 Gate Triggering Mode 2 747
884 [dV/dt] Capability 748
8 9 Summary 749
References 752
9 Insulated Gate Bipolar Transistors 755
9 1 Basic Device Structures 759
9 2 Device Operation and Output Characteristics 763
9 3 Device Equivalent Circuits 765
9 4 Blocking Characteristics 766
941 Symmetric Structure Forward Blocking
Capability 767
942 Symmetric Structure Reverse Blocking
Capability 770
XXVI
Contents
943 Symmetric Structure Leakage Current 772
944 Asymmetric Structure Forward Blocking
Capability 778
945 Asymmetric Structure Reverse Blocking
Capability 785
946 Asymmetric Structure Leakage Current 787
9 5 On-State Characteristics 794
951 On-State Model 795
952 On-Stale Carrier Distribution: Symmetric
Structure 802
953 On-State Voltage Drop: Symmetric Structure 809
954 On-State Carrier Distribution: Asymmetric
Structure 813
955 On-State Voltage Drop: Asymmetric Structure 820
956 On-State Carrier Distribution: Transparent Emitter
Structure 825
957 On-State Voltage Drop: Transparent Emitter
Structure 831
9 6 Current Saturation Model 833
961 Carrier Distribution: Symmetric Structure 838
962 Output Characteristics: Symmetric Structure 846
963 Output Resistance: Symmetric Structure 851
964 Carrier Distribution: Asymmetric Structure 852
965 Output Characteristics: Asymmetric Structure 862
966 Output Resistance: Asymmetric Structure 866
967 Carrier Distribution: Transparent Emitter Structure 867
968 Output Characteristics: Transparent Emitter
Structure 870
969 Output Resistance: Transparent Emitter Structure 874
9 7 Switching Characteristics 874
971 Tum-On Physics: Forward Recovery 876
972 Turn-Off Physics: No-Load Conditions 883
973 Turn-Off Physics: Resistive Load 885
974 Turn-Off Physics: Inductive Load 894
975 Energy Loss per Cycle 922
9 8 Power-Loss Optimization 925
981 Symmetric Structure 925
982 Asymmetric Structure 927
983 Transparent Emitter Structure 928
984 Comparison of Trade-Off Curves 930
9 9 Complementary (p-Channel) Structure 931
991 On-Stale Characteristics 934
992 Switching Characteristics 936
993 Power-Loss Optimization 938
Contents xxvii
9 10 Latch-Up Suppression 939
9 10 1 Deep P* Diffusion 940
9 10 2 Shallow P-Layer 946
9 10 3 Reduced Gate Oxide Thickness 949
9 10 4 Bipolar Current Bypass 954
9 10 5 Diverter Structure 958
9 10 6 Cell Topology 960
9 10 7 Latch-Up Proof Structure 966
9 11 Safe Operating Area 969
9 11 1 Forward-Biased Safe Operating Area 970
9 11 2 Reverse-Biased Safe Operating Area 974
9 11 3 Short-Circuit Safe Operating Area 978
9 12 Trench-Gate Structure 984
9 12 1 Blocking Mode 985
9 12 2 On-State Carrier Distribution 986
9 12 3 On-State Voltage Drop 988
9 12 4 Switching Characteristics 990
9 12 5 Safe Operating Area 991
9 12 6 Modified Structures 996
9 13 Blocking Voltage Scaling 998
9 13 1 N-Base Design 998
9 13 2 Power MOSFET Baseline 1000
9 13 3 On-State Characteristics 1000
9 13 4 Trade-Off Curve 1003
9 14 High-Temperature Operation 1004
9 14 1 On-State Characteristics 1004
9 14 2 Latch-Up Characteristics 1007
9 15 Lifetime Control Techniques 1009
9 15 1 Electron Irradiation 1010
9 15 2 Neutron Irradiation 1011
9 15 3 Helium Irradiation 1012
9 16 Cell Optimization 1012
9 16 1 Planar-Gate Structure 1013
9 16 2 Trench-Gate Structure 1017
9 17 Reverse Conducting Structure 1024
9 18 SoftSwitching 1032
9 19 Summary 1036
References 1041
10 Synopsis 1045
10 1 Typical H-Bridge Topology 1045
10 2 Power-Loss Analysis 1047
10 3 Low DC-Bus Voltage Applications 1050
10 4 Medium DC-Bus Voltage Applications 1054
Contents
xxvni
10 5 High DC-Bus Voltage Applications
10 6 Social Impact
10 7 Summary
References
1058
1062
1064
1065
Index
|
| any_adam_object | 1 |
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| indexdate | 2024-07-10T08:37:26Z |
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| isbn | 9783319939872 |
| language | English |
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| physical | xxxii, 1086 Seiten Illustrationen, Diagramme |
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| publisher | Springer |
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| spelling | Baliga, B. Jayant 1948- Verfasser (DE-588)136919014 aut Fundamentals of power semiconductor devices B. Jayant Baliga Second edition Cham Springer [2019] xxxii, 1086 Seiten Illustrationen, Diagramme txt rdacontent n rdamedia nc rdacarrier Leistungshalbleiter (DE-588)4167286-0 gnd rswk-swf Leistungselektronik (DE-588)4035235-3 gnd rswk-swf Leistungselektronik (DE-588)4035235-3 s Leistungshalbleiter (DE-588)4167286-0 s DE-604 Erscheint auch als Online-Ausgabe 978-3-319-93988-9 HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=031558646&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Baliga, B. Jayant 1948- Fundamentals of power semiconductor devices Leistungshalbleiter (DE-588)4167286-0 gnd Leistungselektronik (DE-588)4035235-3 gnd |
| subject_GND | (DE-588)4167286-0 (DE-588)4035235-3 |
| title | Fundamentals of power semiconductor devices |
| title_auth | Fundamentals of power semiconductor devices |
| title_exact_search | Fundamentals of power semiconductor devices |
| title_full | Fundamentals of power semiconductor devices B. Jayant Baliga |
| title_fullStr | Fundamentals of power semiconductor devices B. Jayant Baliga |
| title_full_unstemmed | Fundamentals of power semiconductor devices B. Jayant Baliga |
| title_short | Fundamentals of power semiconductor devices |
| title_sort | fundamentals of power semiconductor devices |
| topic | Leistungshalbleiter (DE-588)4167286-0 gnd Leistungselektronik (DE-588)4035235-3 gnd |
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